OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [busmaster.v] - Diff between revs 33 and 34

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 33 Rev 34
Line 48... Line 48...
`define ICAPE_ACCESS
`define ICAPE_ACCESS
`endif
`endif
`define FLASH_ACCESS
`define FLASH_ACCESS
`define SDRAM_ACCESS
`define SDRAM_ACCESS
`define GPS_CLOCK
`define GPS_CLOCK
 
`ifdef  VERILATOR
 
`define GPSTB
 
`endif
//      UART_ACCESS and GPS_UART have both been placed within fastio
//      UART_ACCESS and GPS_UART have both been placed within fastio
//              `define UART_ACCESS
//              `define UART_ACCESS
//              `define GPS_UART
//              `define GPS_UART
`define RTC_ACCESS
`define RTC_ACCESS
`define OLEDRGB_ACCESS
`define OLEDRGB_ACCESS
Line 654... Line 657...
                        scop_int, flash_int, rtc_pps };
                        scop_int, flash_int, rtc_pps };
        wire    [5:0]    board_ints;
        wire    [5:0]    board_ints;
        wire    [3:0]    w_led;
        wire    [3:0]    w_led;
        wire    rtc_ppd;
        wire    rtc_ppd;
        fastio  #(
        fastio  #(
                .AUXUART_SETUP(30'hd705),        // 115200 Baud, 8N1, from 81.25M
                .AUXUART_SETUP(30'd705), // 115200 Baud, 8N1, from 81.25M
                .GPSUART_SETUP(30'hd8464),       //   9600 Baud, 8N1
                .GPSUART_SETUP(30'd8464),        //   9600 Baud, 8N1
                .EXTRACLOCK(0)
                .EXTRACLOCK(0)
                ) runio(i_clk, i_sw, i_btn,
                ) runio(i_clk, i_sw, i_btn,
                        w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
                        w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
                        i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
                        i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
                        wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
                        wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
                                wb_data, io_ack, io_stall, io_data,
                                wb_data, io_ack, io_stall, io_data,
                        rtc_ppd,
                        rtc_ppd,
                        bus_err_addr, master_ints, w_interrupt,
                        bus_err_addr, gps_now[63:32], gps_step[47:16], master_ints, w_interrupt,
                        board_ints);
                        board_ints);
        assign  { gpio_int, auxrx_int, auxtx_int, gpsrx_int, sw_int, btn_int } = board_ints;
        assign  { gpio_int, auxrx_int, auxtx_int, gpsrx_int, sw_int, btn_int } = board_ints;
 
 
        /*
        /*
        reg     [25:0]  dbg_counter_err, dbg_counter_cyc, dbg_counter_sel,
        reg     [25:0]  dbg_counter_err, dbg_counter_cyc, dbg_counter_sel,

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.