///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zipcpu.v
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// Filename: zipcpuhs.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: This is the top level module holding the core of the Zip CPU
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// Purpose: This is the top level module holding the core of the Zip CPU
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// together. The Zip CPU is designed to be as simple as possible.
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// together. The Zip CPU is designed to be as simple as possible.
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// (actual implementation aside ...) The instruction set is about as
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// (actual implementation aside ...) The instruction set is about as
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// RISC as you can get, there are only 16 instruction types supported.
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// RISC as you can get, there are only 26 instruction types supported, not
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// Please see the accompanying spec.pdf file for a description of these
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// including the floating point instruction set. Please see the
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// instructions.
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// accompanying spec.pdf file for a description of these instructions.
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//
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//
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// All instructions are 32-bits wide. All bus accesses, both address and
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// All instructions are 32-bits wide. All bus accesses, both address and
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// data, are 32-bits over a wishbone bus.
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// data, are 32-bits over a wishbone bus.
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//
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//
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// The Zip CPU is fully pipelined with the following pipeline stages:
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//
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// This version of the ZipCPU has been modified for "high speed" operation.
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// By that I mean, it has been modified so that it can handle a high speed
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// system clock. The nominal five stage pipeline has therefore been
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// broken into nine pieces, as outlined below:
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//
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//
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// 1. Prefetch, returns the instruction from memory.
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// 1. Prefetch, returns the instruction from memory.
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//
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//
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// 2. Instruction Decode
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// 2. Instruction Decode: triplet instructions, VLIW upper half,
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// VLIW lower half, and normal instructions
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//
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//
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// 3. Read Operands
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// 3. Instruction Decode: Select among the four types of
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// instructions
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//
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//
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// 4. Apply Instruction
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// 4. Read Operand B
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//
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//
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// 4. Write-back Results
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// 5. Read Operand A, add the immediate offset to Operand B
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//
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//
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// Further information about the inner workings of this CPU may be
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// 6. 16 ALU operations
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// found in the spec.pdf file. (The documentation within this file
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// had become out of date and out of sync with the spec.pdf, so look
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// to the spec.pdf for accurate and up to date information.)
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//
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//
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// 7. Select among ALU results
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//
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//
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// In general, the pipelining is controlled by three pieces of logic
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// 8. Select from ALU, Memory, Divide, FPU results
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// per stage: _ce, _stall, and _valid. _valid means that the stage
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// holds a valid instruction. _ce means that the instruction from the
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// previous stage is to move into this one, and _stall means that the
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// instruction from the previous stage may not move into this one.
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// The difference between these control signals allows individual stages
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// to propagate instructions independently. In general, the logic works
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// as:
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//
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//
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// 9. Write-back Results
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//
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//
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// assign (n)_ce = (n-1)_valid && (~(n)_stall)
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// Further information about the ZipCPU may be found in the spec.pdf file.
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// (The documentation within this file is likely to become out of date
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// and out of sync with the spec.pdf, so look to the spec.pdf for
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// accurate and up to date information.)
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//
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//
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//
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//
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// always @(posedge i_clk)
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// A note about pipelining. The approach used to accommodate pipelining
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// if ((i_rst)||(clear_pipeline))
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// in this implementation assumes that if will be impossible to tell if
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// (n)_valid = 0
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// a particular stage will stall until the logic for that stage completes.
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// else if (n)_ce
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// There is no time, therefore, for the stall logic to ripple from the
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// (n)_valid = 1
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// end of the pipeline to the beginning. At best, it can ripple from
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// else if (n+1)_ce
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// one stage to the next. Stall logic, therefore, is latched in a
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// (n)_valid = 0
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// FLIP-FLOP, rather than done in a combinatorial fashion. Hopefully,
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// you'll have a copy of the stall logic slides. If not, here's the
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// outline of how stalls will be done:
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//
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//
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// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) )
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// assign (n)_slp = // stall logic for location n, based upon the prior
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// || ( (n)_valid && (n+1)_stall );
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// // stages info
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// assign (n)_slc = // stall logic for location n, based upon a copy of
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// // what was in the prior stage
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//
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//
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// and ...
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//
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//
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// // We'll shorten _valid to _v, _stall to _s, _copy to _c
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// always @(posedge i_clk)
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// always @(posedge i_clk)
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// if (n)_ce
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// if ((i_rst)||(clear_pipeline)
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// (n)_variable = ... whatever logic for this stage
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// (n)_v = 0;
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// else if (!(n)_stall)
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// (n)_v = ( (n-1)_v && (!(n)_slp) );
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// else
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// (n)_v = ( !(n)_slc );
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//
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//
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// Note that a stage can stall even if no instruction is loaded into
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// always @(posedge i_clk)
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// it.
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// if ((i_rst)||(clear_pipeline)
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// (n)_s = 1'b0;
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// else if (!(n)_s)
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// (n)_s = ((n-1)_v) && ( (n)_slp || (n+1)_s );
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// else
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// (n)_s = ( (n)_slc || (n+1)_s );
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//
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// always @(posedge i_clk)
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// if ((n)_s)
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// (n)_data = PROCESS[(n)_c];
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// // Can't chnge copy if not stalled
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// else
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// (n)_data = PROCESS[(n-1)_data];
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// (n)_c <= (n-1)_data;
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// We can either pipeline our fetches, or issue one fetch at a time. Pipelined
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// We can either pipeline our fetches, or issue one fetch at a time. Pipelined
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// fetches are more complicated and therefore use more FPGA resources, while
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// fetches are more complicated and therefore use more FPGA resources, while
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// single fetches will cause the CPU to stall for about 5 stalls each
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// single fetches will cause the CPU to stall for about 5 stalls each
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// instruction cycle, effectively reducing the instruction count per clock to
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// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2. However, the area cost may be worth it. Consider:
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// about 0.2. However, the area cost may be worth it. Consider:
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//
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//
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// Slice LUTs ZipSystem ZipCPU
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// Slice LUTs ZipSystem ZipCPU
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// Single Fetching 2521 1734
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// Single Fetching 2521 1734
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// Pipelined fetching 2796 2046
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// Pipelined fetching 2796 2046
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//
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//
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//
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//
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//
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//
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`define CPU_CC_REG 4'he
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`define CPU_CC_REG 4'he
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`define CPU_PC_REG 4'hf
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`define CPU_PC_REG 4'hf
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`define CPU_CLRCACHE_BIT 14 // Floating point error flag, set on error
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`define CPU_CLRCACHE_BIT 14 // Floating point error flag, set on error
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`define CPU_PHASE_BIT 13 // Floating point error flag, set on error
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`define CPU_PHASE_BIT 13 // Floating point error flag, set on error
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`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
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`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
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`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
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`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
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`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
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`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
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`define CPU_TRAP_BIT 9 // User TRAP has taken place
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`define CPU_TRAP_BIT 9 // User TRAP has taken place
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`define CPU_ILL_BIT 8 // Illegal instruction
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`define CPU_ILL_BIT 8 // Illegal instruction
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`define CPU_BREAK_BIT 7
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`define CPU_BREAK_BIT 7
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`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions
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`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT 5
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`define CPU_GIE_BIT 5
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`define CPU_SLEEP_BIT 4
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`define CPU_SLEEP_BIT 4
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// Compile time defines
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// Compile time defines
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//
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//
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`include "cpudefs.v"
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`include "cpudefs.v"
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//
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//
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//
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//
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module zipcpuhs(i_clk, i_rst, i_interrupt,
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module zipcpuhs(i_clk, i_rst, i_interrupt,
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// Debug interface
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// Debug interface
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i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
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i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_break,
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o_break,
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// CPU interface to the wishbone bus
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// CPU interface to the wishbone bus
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o_wb_gbl_cyc, o_wb_gbl_stb,
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o_wb_gbl_cyc, o_wb_gbl_stb,
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o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_err,
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i_wb_err,
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// Accounting/CPU usage interface
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// Accounting/CPU usage interface
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o_op_stall, o_pf_stall, o_i_count
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o_op_stall, o_pf_stall, o_i_count
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_debug
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, o_debug
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`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
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LGICACHE=6;
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LGICACHE=6;
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`ifdef OPT_MULTIPLY
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`ifdef OPT_MULTIPLY
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parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
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parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
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`else
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`else
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parameter IMPLEMENT_MPY = 0;
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parameter IMPLEMENT_MPY = 0;
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`endif
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`endif
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`ifdef OPT_DIVIDE
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`ifdef OPT_DIVIDE
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parameter IMPLEMENT_DIVIDE = 1;
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parameter IMPLEMENT_DIVIDE = 1;
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`else
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`else
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parameter IMPLEMENT_DIVIDE = 0;
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parameter IMPLEMENT_DIVIDE = 0;
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`endif
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`endif
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`ifdef OPT_IMPLEMENT_FPU
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`ifdef OPT_IMPLEMENT_FPU
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parameter IMPLEMENT_FPU = 1,
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parameter IMPLEMENT_FPU = 1,
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`else
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`else
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parameter IMPLEMENT_FPU = 0,
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parameter IMPLEMENT_FPU = 0,
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`endif
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`endif
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IMPLEMENT_LOCK=1;
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IMPLEMENT_LOCK=1;
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`ifdef OPT_EARLY_BRANCHING
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`ifdef OPT_EARLY_BRANCHING
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parameter EARLY_BRANCHING = 1;
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parameter EARLY_BRANCHING = 1;
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`else
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`else
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parameter EARLY_BRANCHING = 0;
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parameter EARLY_BRANCHING = 0;
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`endif
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`endif
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parameter AW=ADDRESS_WIDTH;
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parameter AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_interrupt;
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input i_clk, i_rst, i_interrupt;
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// Debug interface -- inputs
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// Debug interface -- inputs
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input i_halt, i_clear_pf_cache;
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input i_halt, i_clear_pf_cache;
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input [4:0] i_dbg_reg;
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input [4:0] i_dbg_reg;
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input i_dbg_we;
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input i_dbg_we;
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input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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// Debug interface -- outputs
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// Debug interface -- outputs
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output wire o_dbg_stall;
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output wire o_dbg_stall;
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output reg [31:0] o_dbg_reg;
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output reg [31:0] o_dbg_reg;
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output reg [3:0] o_dbg_cc;
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output reg [3:0] o_dbg_cc;
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output wire o_break;
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output wire o_break;
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// Wishbone interface -- outputs
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// Wishbone interface -- outputs
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output wire o_wb_gbl_cyc, o_wb_gbl_stb;
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output wire o_wb_gbl_cyc, o_wb_gbl_stb;
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output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
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output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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// Wishbone interface -- inputs
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// Wishbone interface -- inputs
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_wb_err;
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input i_wb_err;
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// Accounting outputs ... to help us count stalls and usage
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// Accounting outputs ... to help us count stalls and usage
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output wire o_op_stall;
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output wire o_op_stall;
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output wire o_pf_stall;
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output wire o_pf_stall;
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output wire o_i_count;
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output wire o_i_count;
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//
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//
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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output reg [31:0] o_debug;
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output reg [31:0] o_debug;
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`endif
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`endif
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// Registers
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// Registers
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//
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//
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// The distributed RAM style comment is necessary on the
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// The distributed RAM style comment is necessary on the
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// SPARTAN6 with XST to prevent XST from oversimplifying the register
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// SPARTAN6 with XST to prevent XST from oversimplifying the register
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// set and in the process ruining everything else. It basically
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// set and in the process ruining everything else. It basically
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// optimizes logic away, to where it no longer works. The logic
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// optimizes logic away, to where it no longer works. The logic
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// as described herein will work, this just makes sure XST implements
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// as described herein will work, this just makes sure XST implements
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// that logic.
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// that logic.
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//
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//
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(* ram_style = "distributed" *)
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(* ram_style = "distributed" *)
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reg [31:0] regset [0:31];
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reg [31:0] regset [0:31];
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// Condition codes
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// Condition codes
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// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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reg [3:0] flags, iflags;
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reg [3:0] flags, iflags;
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wire [14:0] w_uflags, w_iflags;
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wire [14:0] w_uflags, w_iflags;
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reg trap, break_en, step, gie, sleep, r_halted,
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reg trap, break_en, step, gie, sleep, r_halted,
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break_pending;
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break_pending;
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wire w_clear_icache;
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wire w_clear_icache;
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`ifdef OPT_ILLEGAL_INSTRUCTION
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`ifdef OPT_ILLEGAL_INSTRUCTION
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reg ill_err_u, ill_err_i;
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reg ill_err_u, ill_err_i;
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`else
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`else
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wire ill_err_u, ill_err_i;
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wire ill_err_u, ill_err_i;
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`endif
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`endif
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reg ubreak;
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reg ubreak;
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reg ibus_err_flag, ubus_err_flag;
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reg ibus_err_flag, ubus_err_flag;
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wire idiv_err_flag, udiv_err_flag;
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wire idiv_err_flag, udiv_err_flag;
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wire ifpu_err_flag, ufpu_err_flag;
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wire ifpu_err_flag, ufpu_err_flag;
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wire ihalt_phase, uhalt_phase;
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wire ihalt_phase, uhalt_phase;
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// The master chip enable
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// The master chip enable
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wire master_ce;
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wire master_ce;
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//
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//
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//
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//
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// PIPELINE STAGE #1 :: Prefetch
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// PIPELINE STAGE #1 :: Prefetch
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// Variable declarations
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// Variable declarations
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//
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//
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reg [(AW-1):0] pf_pc;
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reg [(AW-1):0] pf_pc;
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reg new_pc;
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reg new_pc;
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wire clear_pipeline;
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wire clear_pipeline;
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assign clear_pipeline = new_pc;
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assign clear_pipeline = new_pc;
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wire dcd_stalled;
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wire dcd_stalled;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
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wire [(AW-1):0] pf_addr;
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wire [(AW-1):0] pf_addr;
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wire [31:0] pf_data;
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wire [31:0] pf_data;
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wire [31:0] instruction;
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wire [31:0] instruction;
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wire [(AW-1):0] instruction_pc;
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wire [(AW-1):0] instruction_pc;
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wire pf_valid, instruction_gie, pf_illegal;
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wire pf_v, instruction_gie, pf_illegal;
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//
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//
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//
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//
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// PIPELINE STAGE #2 :: Instruction Decode
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// PIPELINE STAGE #2 :: Instruction Decode
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// Variable declarations
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// Variable declarations
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//
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//
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//
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//
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wire op_stall, dcd_ce, dcd_phase;
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wire op_stall, dcd_ce, dcd_phase;
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wire [3:0] dcdOp;
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wire [3:0] dcdOp;
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wire [4:0] dcd_iA, dcd_iB, dcd_iR;
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wire [4:0] dcd_iA, dcd_iB, dcd_iR;
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wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
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wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
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wire [3:0] dcdF;
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wire [3:0] dcdF;
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wire dcd_wR, dcd_rA, dcd_rB,
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wire dcd_wR, dcd_rA, dcd_rB,
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dcdALU, dcdM, dcdDV, dcdFP,
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dcdALU, dcdM, dcdDV, dcdFP,
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dcdF_wr, dcd_gie, dcd_break, dcd_lock,
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dcdF_wr, dcd_gie, dcd_break, dcd_lock,
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dcd_pipe, dcd_ljmp;
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dcd_pipe, dcd_ljmp;
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reg [1:0] r_dcdvalid;
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reg [1:0] r_dcdvalid;
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wire dcd_valid;
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wire dcd_v;
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wire [(AW-1):0] dcd_pc;
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wire [(AW-1):0] dcd_pc;
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wire [31:0] dcd_I;
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wire [31:0] dcd_I;
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wire dcd_zI; // true if dcdI == 0
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wire dcd_zI; // true if dcdI == 0
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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|
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wire dcd_illegal;
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wire dcd_illegal;
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wire dcd_early_branch;
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wire dcd_early_branch;
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wire [(AW-1):0] dcd_branch_pc;
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wire [(AW-1):0] dcd_branch_pc;
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|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #3a :: Read Operands
|
// PIPELINE STAGE #3a :: Read Operands
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
//
|
//
|
// Now, let's read our operands
|
// Now, let's read our operands
|
reg opa_valid, opa_DV, opa_FP, opa_ALU, opa_M,
|
reg opa_v, opa_DV, opa_FP, opa_ALU, opa_M,
|
opa_rA, opa_rB;
|
opa_rA, opa_rB;
|
reg [4:0] alu_reg;
|
reg [4:0] alu_reg;
|
reg [3:0] opa_opn;
|
reg [3:0] opa_opn;
|
reg [4:0] opa_R, opa_iA;
|
reg [4:0] opa_R, opa_iA;
|
reg [31:0] r_opa_B;
|
reg [31:0] r_opa_B;
|
reg [(AW-1):0] opa_pc;
|
reg [(AW-1):0] opa_pc;
|
wire [31:0] opA_nowait, opa_Bnowait, opa_A, opa_B, opa_I;
|
wire [31:0] opA_nowait, opa_Bnowait, opa_A, opa_B, opa_I;
|
reg opa_wR, opa_ccR, opa_wF, opa_gie;
|
reg opa_wR, opa_ccR, opa_wF, opa_gie;
|
wire [13:0] opa_Fl;
|
wire [13:0] opa_Fl;
|
reg [5:0] r_opa_F;
|
reg [5:0] r_opa_F;
|
wire [7:0] opa_F;
|
wire [7:0] opa_F;
|
wire opa_ce, opa_phase, opa_pipe;
|
wire opa_ce, opa_phase, opa_pipe;
|
// Some pipeline control wires
|
// Some pipeline control wires
|
reg opa_A_alu, opa_A_mem;
|
reg opa_A_alu, opa_A_mem;
|
reg opa_B_alu, opa_B_mem;
|
reg opa_B_alu, opa_B_mem;
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
reg opa_illegal;
|
reg opa_illegal;
|
`else
|
|
wire opa_illegal;
|
|
assign opa_illegal = 1'b0;
|
|
`endif
|
|
reg opa_break;
|
reg opa_break;
|
reg opa_lock;
|
reg opa_lock;
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #3b :: Read Operands
|
// PIPELINE STAGE #3b :: Read Operands
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
//
|
//
|
// Now, let's read our operands
|
// Now, let's read our operands
|
reg [3:0] opb_opn;
|
reg [3:0] opb_opn;
|
reg opb_valid, opb_valid_mem, opb_valid_alu;
|
reg opb_v, opb_v_mem, opb_v_alu;
|
reg opb_valid_div, opb_valid_fpu;
|
reg opb_v_div, opb_v_fpu;
|
reg [4:0] opb_R;
|
reg [4:0] opb_R;
|
reg [31:0] r_opb_A, r_opb_B;
|
reg [31:0] r_opb_A, r_opb_B;
|
reg [(AW-1):0] opb_pc;
|
reg [(AW-1):0] opb_pc;
|
wire [31:0] opb_A_nowait, opb_B_nowait, opb_A, opb_B;
|
wire [31:0] opb_A_nowait, opb_B_nowait, opb_A, opb_B;
|
reg opb_wR, opb_ccR, opb_wF, opb_gie;
|
reg opb_wR, opb_ccR, opb_wF, opb_gie;
|
wire [13:0] opb_Fl;
|
wire [13:0] opb_Fl;
|
reg [5:0] r_opb_F;
|
reg [5:0] r_opb_F;
|
wire [7:0] opb_F;
|
wire [7:0] opb_F;
|
wire opb_ce, opb_phase, opb_pipe;
|
wire opb_ce, opb_phase, opb_pipe;
|
// Some pipeline control wires
|
// Some pipeline control wires
|
reg opb_A_alu, opb_A_mem;
|
reg opb_A_alu, opb_A_mem;
|
reg opb_B_alu, opb_B_mem;
|
reg opb_B_alu, opb_B_mem;
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
reg opb_illegal;
|
reg opb_illegal;
|
`else
|
|
wire opb_illegal;
|
|
assign opb_illegal = 1'b0;
|
|
`endif
|
|
reg opb_break;
|
reg opb_break;
|
reg opb_lock;
|
reg opb_lock;
|
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory / Divide
|
// PIPELINE STAGE #4 :: ALU / Memory / Divide
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
|
reg stage_busy;
|
reg [(AW-1):0] alu_pc;
|
reg [(AW-1):0] alu_pc;
|
reg r_alu_pc_valid, mem_pc_valid;
|
reg r_alu_pc_v, mem_pc_v;
|
wire alu_pc_valid;
|
wire alu_pc_v;
|
wire alu_phase;
|
wire alu_phase;
|
wire alu_ce, alu_stall;
|
wire alu_ce, alu_stall;
|
wire [31:0] alu_result;
|
wire [31:0] alu_result;
|
wire [3:0] alu_flags;
|
wire [3:0] alu_flags;
|
wire alu_valid, alu_busy;
|
wire alu_v, alu_busy;
|
wire set_cond;
|
wire set_cond;
|
reg alu_wr, alF_wr, alu_gie;
|
reg alu_wr, alF_wr, alu_gie;
|
wire alu_illegal_op;
|
wire alu_illegal_op;
|
wire alu_illegal;
|
wire alu_illegal;
|
|
|
|
|
|
|
wire mem_ce, mem_stalled;
|
wire mem_ce, mem_stalled;
|
wire mem_pipe_stalled;
|
wire mem_pipe_stalled;
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
wire mem_v, mem_ack, mem_stall, mem_err, bus_err,
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
wire [4:0] mem_wreg;
|
wire [4:0] mem_wreg;
|
|
|
wire mem_busy, mem_rdbusy;
|
wire mem_busy, mem_rdbusy;
|
wire [(AW-1):0] mem_addr;
|
wire [(AW-1):0] mem_addr;
|
wire [31:0] mem_data, mem_result;
|
wire [31:0] mem_data, mem_result;
|
|
|
wire div_ce, div_error, div_busy, div_valid;
|
wire div_ce, div_error, div_busy, div_v;
|
wire [31:0] div_result;
|
wire [31:0] div_result;
|
wire [3:0] div_flags;
|
wire [3:0] div_flags;
|
|
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opb_valid_div)
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opb_v_div)
|
&&(~stage_busy)&&(set_cond);
|
&&(~stage_busy)&&(set_cond);
|
|
|
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
|
wire fpu_ce, fpu_error, fpu_busy, fpu_v;
|
wire [31:0] fpu_result;
|
wire [31:0] fpu_result;
|
wire [3:0] fpu_flags;
|
wire [3:0] fpu_flags;
|
|
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opb_valid_fpu)
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opb_v_fpu)
|
&&(~stage_busy)&&(set_cond);
|
&&(~stage_busy)&&(set_cond);
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #5 :: Write-back
|
// PIPELINE STAGE #5 :: Write-back
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
|
wire [4:0] wr_reg_id;
|
wire [4:0] wr_reg_id;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
reg [(AW-1):0] upc, ipc;
|
reg [(AW-1):0] upc, ipc;
|
|
|
|
|
|
|
//
|
//
|
// MASTER: clock enable.
|
// MASTER: clock enable.
|
//
|
//
|
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep);
|
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep);
|
|
|
|
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
// Calculate stall conditions
|
// Calculate stall conditions
|
//
|
//
|
// These are calculated externally, within the prefetch module.
|
// These are calculated externally, within the prefetch module.
|
//
|
//
|
|
|
//
|
//
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline);
|
assign dcd_ce = ((~dcd_v)||(~dcd_stalled))&&(~clear_pipeline);
|
|
|
assign dcd_stalled = (dcd_valid)&&(op_stall);
|
assign dcd_stalled = (dcd_v)&&(opa_stall);
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
|
// PIPELINE STAGE #3 :: Read Operands
|
// Calculate stall conditions
|
// Calculate stall conditions
|
wire op_lock_stall;
|
wire op_lock_stall;
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
|
assign opa_stall_slp = (
|
// Stall if we're stopped, and not allowed to execute
|
|
// an instruction
|
|
// (~master_ce) // Already captured in alu_stall
|
|
//
|
|
// Stall if going into the ALU and the ALU is stalled
|
|
// i.e. if the memory is busy, or we are single
|
|
// stepping. This also includes our stalls for
|
|
// op_break and op_lock, so we don't need to
|
|
// include those as well here.
|
|
// This also includes whether or not the divide or
|
|
// floating point units are busy.
|
|
(alu_stall)
|
|
//
|
|
// Stall if we are going into memory with an operation
|
|
// that cannot be pipelined, and the memory is
|
|
// already busy
|
|
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
|
|
)
|
|
||(dcd_valid)&&(
|
|
// Stall if we need to wait for an operand A
|
|
// to be ready to read
|
|
(dcdA_stall)
|
|
// Likewise for B, also includes logic
|
// Likewise for B, also includes logic
|
// regarding immediate offset (register must
|
// regarding immediate offset (register must
|
// be in register file if we need to add to
|
// be in register file if we need to add to
|
// an immediate)
|
// an immediate)
|
||(dcdB_stall)
|
(((dcdB_rd)&&(~dcd_zI))
|
|
&&((opa_v)&&(opb_R == dcdB)
|
|
||(mem_rdbusy)
|
|
||((div_busy)&&(div_R == dcdB))
|
|
||((fpu_busy)&&(fpu_R == dcdB))
|
|
||((alua_v)&&(alua_R==dcdB))
|
|
||((alub_v)&&(alub_R==dcdB))
|
|
||((alu_busy))
|
|
&&(
|
|
// 1.
|
|
((~dcd_zI)&&(
|
|
((opb_R == dcdB)&&(opb_wR))
|
|
||((mem_rdbusy)&&(~dcd_pipe))
|
|
))
|
|
// 2.
|
|
||((opF_wr)&&(dcdB_cc))
|
|
)))
|
// Or if we need to wait on flags to work on the
|
// Or if we need to wait on flags to work on the
|
// CC register
|
// CC register
|
||(dcdF_stall)
|
||(((~dcdF[3])
|
|
||((dcd_rA)&&(dcdA_cc))
|
|
||((dcd_rB)&&(dcdB_cc)))
|
|
&&(opb_v)&&(opb_ccR))
|
);
|
);
|
assign opa_ce = ((dcd_valid)||(dcd_illegal))&&(~opa_stall);
|
|
|
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// Calculate stall conditions
|
// Calculate stall conditions
|
//
|
//
|
// 1. Basic stall is if the previous stage is valid and the next is
|
// 1. Basic stall is if the previous stage is valid and the next is
|
// busy.
|
// busy.
|
// 2. Also stall if the prior stage is valid and the master clock enable
|
// 2. Also stall if the prior stage is valid and the master clock enable
|
// is de-selected
|
// is de-selected
|
// 3. Stall if someone on the other end is writing the CC register,
|
// 3. Stall if someone on the other end is writing the CC register,
|
// since we don't know if it'll put us to sleep or not.
|
// since we don't know if it'll put us to sleep or not.
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// through the ALU. Break instructions are not allowed through
|
// through the ALU. Break instructions are not allowed through
|
// the ALU.
|
// the ALU.
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
assign alu_stall_clp = (~master_ce);
|
// Old case #3--this isn't an ALU stall though ...
|
assign alu_stall_cls = (~master_ce);
|
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
always @(posedge i_clk)
|
&&(wr_write_cc)) // Case 3
|
stage_busy <= (alu_ce)||(mem_ce)||(fpu_ce)||(div_ce)
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
||(alu_busy)||(mem_rdbusy)||(fpu_busy)||(div_busy);
|
||((opvalid)&&(op_break))
|
|
||(div_busy)||(fpu_busy);
|
|
assign alu_ce = (master_ce)&&(stage_ce)&&(opvalid_alu)&&(~clear_pipeline);
|
|
assign stage_ce = (~div_busy)&&(~alu_busy)&&(~mem_rdbusy)&&(~fpu_busy);
|
assign stage_ce = (~div_busy)&&(~alu_busy)&&(~mem_rdbusy)&&(~fpu_busy);
|
//
|
//
|
|
|
//
|
//
|
// Note: if you change the conditions for mem_ce, you must also change
|
// Note: if you change the conditions for mem_ce, you must also change
|
// alu_pc_valid.
|
// alu_pc_v.
|
//
|
//
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
|
assign mem_ce = (master_ce)&&(opb_v_mem)&&(~mem_stalled)
|
&&(~clear_pipeline);
|
&&(~clear_pipeline);
|
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
|
assign mem_stall_clp = (~master_ce)||(alu_busy)||(div_busy)||(fpu_busy)
|
|
||(wr_write_pc)||(wr_write_cc)
|
|
||((opb_v_mem)&&(
|
(mem_pipe_stalled)
|
(mem_pipe_stalled)
|
||((~op_pipe)&&(mem_busy))
|
||((~opb_pipe)&&(mem_busy))));
|
||(div_busy)
|
assign mem_stall_cls = (~master_ce)||(alu_busy)||(div_busy)||(fpu_busy)
|
||(fpu_busy)
|
||(wr_write_pc)||(wr_write_cc)
|
// Stall waiting for flags to be valid
|
||((cp_opb_v_mem)&&(
|
// Or waiting for a write to the PC register
|
(mem_pipe_stalled)
|
// Or CC register, since that can change the
|
||((~cp_opb_pipe)&&(mem_busy))));
|
// PC as well
|
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
|
&&((wr_write_pc)||(wr_write_cc)))));
|
|
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
//
|
//
|
//
|
//
|
fastcache #(LGICACHE, ADDRESS_WIDTH)
|
fastcache #(LGICACHE, ADDRESS_WIDTH)
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
i_clear_pf_cache,
|
i_clear_pf_cache,
|
// dcd_pc,
|
// dcd_pc,
|
~dcd_stalled,
|
~dcd_stalled,
|
((dcd_early_branch)&&(~clear_pipeline))
|
((dcd_early_branch)&&(~clear_pipeline))
|
? dcd_branch_pc:pf_pc,
|
? dcd_branch_pc:pf_pc,
|
instruction, instruction_pc, pf_valid,
|
instruction, instruction_pc, pf_v,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_illegal);
|
pf_illegal);
|
assign instruction_gie = gie;
|
assign instruction_gie = gie;
|
|
|
//
|
//
|
// The ifastdec decoder takes two clocks to decode an instruction.
|
// The ifastdec decoder takes two clocks to decode an instruction.
|
// Therefore, to determine if a decoded instruction is valid, we
|
// Therefore, to determine if a decoded instruction is valid, we
|
// need to wait two clocks from pf_valid. Hence, we dump this into
|
// need to wait two clocks from pf_v. Hence, we dump this into
|
// a pipeline below.
|
// a pipeline below.
|
//
|
//
|
initial r_dcdvalid = 2'b00;
|
initial r_dcdvalid = 2'b00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
|
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
|
r_dcdvalid <= 2'b00;
|
r_dcdvalid <= 2'b00;
|
else if (dcd_ce)
|
else if (dcd_ce)
|
r_dcdvalid <= { r_dcdvalid[0], pf_valid };
|
r_dcdvalid <= { r_dcdvalid[0], pf_v };
|
else if (opa_ce)
|
else if (opa_ce)
|
r_dcdvalid <= 1'b0;
|
r_dcdvalid <= 1'b0;
|
assign dcd_valid = r_dcdvalid[1];
|
assign dcd_v = r_dcdvalid[1];
|
|
|
ifastdec #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
ifastdec #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
IMPLEMENT_FPU)
|
IMPLEMENT_FPU)
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
dcd_ce, dcd_stalled, instruction, instruction_gie,
|
dcd_ce, dcd_stalled, instruction, instruction_gie,
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
instruction_pc, pf_v, pf_illegal, dcd_phase,
|
dcd_illegal, dcd_pc, dcd_gie,
|
dcd_illegal, dcd_pc, dcd_gie,
|
{ dcdR_cc, dcdR_pc, dcd_iR },
|
{ dcd_Rcc, dcd_Rpc, dcd_iR },
|
{ dcdA_cc, dcdA_pc, dcd_iA },
|
{ dcd_Acc, dcd_Apc, dcd_iA },
|
{ dcdB_cc, dcdB_pc, dcd_iB },
|
{ dcd_Bcc, dcd_Bpc, dcd_iB },
|
dcd_I, dcd_zI, dcdF, dcdF_wr, dcdOp,
|
dcd_I, dcd_zI, dcd_F, dcd_wF, dcdOp,
|
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
|
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
|
dcd_wR,dcd_rA, dcd_rB,
|
dcd_wR,dcd_rA, dcd_rB,
|
dcd_early_branch,
|
dcd_early_branch,
|
dcd_branch_pc, dcd_ljmp,
|
dcd_branch_pc, dcd_ljmp,
|
dcd_pipe);
|
dcd_pipe);
|
|
|
reg r_op_pipe;
|
//
|
|
//
|
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
|
//
|
|
//
|
|
|
initial r_op_pipe = 1'b0;
|
reg opa_pipe;
|
|
initial opa_pipe = 1'b0;
|
// To be a pipeable operation, there must be
|
// To be a pipeable operation, there must be
|
// two valid adjacent instructions
|
// two valid adjacent instructions
|
// Both must be memory instructions
|
// Both must be memory instructions
|
// Both must be writes, or both must be reads
|
// Both must be writes, or both must be reads
|
// Both operations must be to the same identical address,
|
// Both operations must be to the same identical address,
|
// or at least a single (one) increment above that address
|
// or at least a single (one) increment above that address
|
//
|
//
|
// However ... we need to know this before this clock, hence this is
|
// However ... we need to know this before this clock, hence this is
|
// calculated in the instruction decoder.
|
// calculated in the instruction decoder.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (!opa_stall)
|
r_op_pipe <= dcd_pipe;
|
begin
|
else if (mem_ce) // Clear us any time an op_ is clocked in
|
opa_v <= dcdvalid&&(~opa_stall_slp);
|
r_op_pipe <= 1'b0;
|
opa_stall <= (dcdvalid)&&(opa_stall_slp);
|
assign op_pipe = r_op_pipe;
|
opa_pipe <= dcd_pipe;
|
|
|
|
opa_wR <= dcd_wR;
|
|
{ opa_Acc, opa_Apc, opa_iA, opa_rA }
|
|
<= { dcd_Acc, dcd_Apc, dcd_iA, dcd_rA };
|
|
{ opa_Bcc, opa_Bpc, opa_iB, opa_rB }
|
|
<= { dcd_Bcc, dcd_Bpc, dcd_iB, dcd_rB };
|
|
|
|
// Register A
|
|
if (dcd_Apc)
|
|
opa_vA <= (dcd_iA[4]==dcd_gie) ? dcd_pc
|
|
: (dcd_iA)?upc : ipc;
|
|
else if (dcd_Acc)
|
|
opa_vA <= (dcd_iA[4])?user_flags_reg
|
|
: supervisor_flags_reg;
|
|
else
|
|
opa_vA <= regset[dcd_iA];
|
|
|
//
|
// Register B
|
//
|
if (!dcd_rB)
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
opa_vB <= 32'h00;
|
//
|
else if (dcd_Bpc)
|
//
|
opa_vB <= (dcd_iB[4]==dcd_gie) ? dcd_pc
|
assign w_opA = regset[dcd_iA];
|
: (dcd_iB)?upc : ipc;
|
assign w_opB = regset[dcd_iB];
|
else if (dcd_Bcc)
|
|
opa_vB <= (dcd_iB[4])?user_flags_reg
|
|
: supervisor_flags_reg;
|
|
else
|
|
opa_vB <= regset[dcd_iB];
|
|
|
|
// Copy
|
|
cp_opa_pc <= dcd_pc;
|
|
cp_opa_gie <= dcd_gie;
|
|
cp_opa_pipe <= dcd_pipe;
|
|
{ cp_opa_Rcc, cp_opa_Rpc, cp_opa_iR }
|
|
<= { dcd_Rcc, dcd_Rpc, dcd_iR };
|
|
{ cp_opa_Acc, cp_opa_Apc, cp_opa_iA }
|
|
<= { dcd_Acc, dcd_Apc, dcd_iA };
|
|
{ cp_opa_Bcc, cp_opa_Bpc, cp_opa_iB }
|
|
<= { dcd_Bcc, dcd_Bpc, dcd_iB };
|
|
end else begin
|
|
opa_v <= (~opa_stall_slc);
|
|
opa_stall <= (opa_stall_slc);
|
|
opa_pipe <= cp_opa_pipe;
|
|
|
|
// Register A
|
|
if (cp_opa_Apc)
|
|
opa_vA <= (cp_opa_iA[4]==cp_opa_gie) ? cp_opa_pc
|
|
: (cp_opa_iA)?upc : ipc;
|
|
else if (dcd_Acc)
|
|
opa_vA <= (cp_opa_iA[4])?user_flags_reg
|
|
: supervisor_flags_reg;
|
|
else
|
|
opa_vA <= regset[cp_opa_iA];
|
|
|
|
// Register B
|
|
if (!cp_opa_rB)
|
|
opa_vB <= 32'h00;
|
|
else if (cp_opa_Bpc)
|
|
opa_vB <= (cp_opa_iB[4]==cp_opa_gie) ? cp_opa_pc
|
|
: (cp_opa_iB)?upc : ipc;
|
|
else if (cp_opa_Bcc)
|
|
opa_vB <= (cp_opa_iB[4])?user_flags_reg
|
|
: supervisor_flags_reg;
|
|
else
|
|
opa_vB <= regset[cp_opa_iB];
|
|
end
|
|
|
wire [8:0] w_cpu_info;
|
wire [8:0] w_cpu_info;
|
assign w_cpu_info = {
|
assign w_cpu_info = {
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
1'b1,
|
1'b1,
|
`else
|
`else
|
1'b0,
|
1'b0,
|
`endif
|
`endif
|
1'b1,
|
1'b1,
|
`ifdef OPT_DIVIDE
|
`ifdef OPT_DIVIDE
|
1'b1,
|
1'b1,
|
`else
|
`else
|
1'b0,
|
1'b0,
|
`endif
|
`endif
|
`ifdef OPT_IMPLEMENT_FPU
|
`ifdef OPT_IMPLEMENT_FPU
|
1'b1,
|
1'b1,
|
`else
|
`else
|
1'b0,
|
1'b0,
|
`endif
|
`endif
|
1'b1, 1'b1,
|
1'b1, 1'b1,
|
`ifdef OPT_EARLY_BRANCHING
|
`ifdef OPT_EARLY_BRANCHING
|
1'b1,
|
1'b1,
|
`else
|
`else
|
1'b0,
|
1'b0,
|
`endif
|
`endif
|
1'b1,
|
1'b1,
|
`ifdef OPT_VLIW
|
`ifdef OPT_VLIW
|
1'b1
|
1'b1
|
`else
|
`else
|
1'b0
|
1'b0
|
`endif
|
`endif
|
};
|
};
|
|
|
wire [31:0] w_pcA_v;
|
|
generate
|
|
if (AW < 32)
|
|
assign w_pcA_v = {{(32-AW){1'b0}}, (dcd_iA[4] == dcd_gie)?dcd_pc:upc };
|
|
else
|
|
assign w_pcA_v = (dcd_iA[4] == dcd_gie)?dcd_pc:upc;
|
|
endgenerate
|
|
|
|
reg [4:0] opa_Aid, opa_Bid;
|
|
reg opa_Ard, opa_Brd;
|
|
always @(posedge i_clk)
|
|
if (opa_ce)
|
|
begin
|
|
opa_iA <= dcd_iA;
|
|
opa_iB <= dcd_iB;
|
|
opa_rA <= dcd_rA;
|
|
opa_rB <= dcd_rB;
|
|
end
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opa_ce)
|
if (opa_ce)
|
begin
|
begin
|
if ((wr_reg_ce)&&(wr_reg_id == dcd_iA))
|
if ((wr_reg_ce)&&(wr_reg_id == dcd_iA))
|
r_opA <= wr_gpreg_vl;
|
r_opA <= wr_gpreg_vl;
|
else if (dcdA_pc)
|
else if (dcdA_pc)
|
r_opA <= w_pcA_v;
|
r_opA <= w_pcA_v;
|
else if (dcdA_cc)
|
else if (dcdA_cc)
|
r_opA <= { w_cpu_info, w_opA[22:15], (dcd_iA[4])?w_uflags:w_iflags };
|
r_opA <= { w_cpu_info, w_opA[22:15], (dcd_iA[4])?w_uflags:w_iflags };
|
else
|
else
|
r_opA <= w_opA;
|
r_opA <= w_opA;
|
end else if ((wr_reg_ce)&&(wr_reg_id == opa_iA)&&(opa_rA))
|
end else if ((wr_reg_ce)&&(wr_reg_id == opa_iA)&&(opa_rA))
|
r_opA <= wr_gpreg_vl;
|
r_opA <= wr_gpreg_vl;
|
|
|
wire [31:0] w_opBnI, w_pcB_v;
|
wire [31:0] w_opBnI, w_pcB_v;
|
generate
|
generate
|
if (AW < 32)
|
if (AW < 32)
|
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
|
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
|
else
|
else
|
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
|
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
|
endgenerate
|
endgenerate
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opa_ce)
|
if (opa_ce)
|
begin
|
begin
|
opa_B <= (~dcdB_rd) ? 32'h00
|
opa_B <= (~dcdB_rd) ? 32'h00
|
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
|
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
|
: ((dcdB_pc) ? w_pcB_v
|
: ((dcdB_pc) ? w_pcB_v
|
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
|
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
|
(dcdB[4])?w_uflags:w_iflags}
|
(dcdB[4])?w_uflags:w_iflags}
|
: w_opB)));
|
: w_opB)));
|
opa_I <= dcd_I;
|
opa_I <= dcd_I;
|
end
|
end
|
|
|
//
|
//
|
// B-Inflight
|
// B-Inflight
|
//
|
//
|
// We cannot read the B register if it is "in-flight", that is if the
|
// We cannot read the B register if it is "in-flight", that is if the
|
// result register of any previous instruction still needs to be written.
|
// result register of any previous instruction still needs to be written.
|
//
|
//
|
// reg [31:0] opa_b_inflight;
|
// reg [31:0] opa_b_inflight;
|
// always @(posedge i_clk)
|
// always @(posedge i_clk)
|
// if ((i_reset)||(clear_pipeline))
|
// if ((i_reset)||(clear_pipeline))
|
// opa_b_inflight <= 32'h00;
|
// opa_b_inflight <= 32'h00;
|
// else begin
|
// else begin
|
// if (wr_reg_ce)
|
// if (wr_reg_ce)
|
// opa_b_inflight[wr_reg_id] <= 1'b0;
|
// opa_b_inflight[wr_reg_id] <= 1'b0;
|
// if (opb_ce)
|
// if (opb_ce)
|
// opa_b_inflight[opa_Rid] <= 1'b1;
|
// opa_b_inflight[opa_Rid] <= 1'b1;
|
// end
|
// end
|
//
|
//
|
// always @(posedge i_clk)
|
// always @(posedge i_clk)
|
// if (opa_b_invalid)
|
// if (opa_b_invalid)
|
// opa_b_invalid <= opa_b_inflight[opa_A];
|
// opa_b_invalid <= opa_b_inflight[opa_A];
|
// else
|
// else
|
// opa_b_invalid <= opa_b_inflight[dcd_iA];
|
// opa_b_invalid <= opa_b_inflight[dcd_iA];
|
//
|
//
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opb_ce)
|
if (opb_ce)
|
opb_B <= opa_B + opa_I;
|
opb_B <= opa_B + opa_I;
|
else if ((wr_reg_ce)&&(opa_Bid == wr_reg_id)&&(opa_Brd))
|
else if ((wr_reg_ce)&&(opa_Bid == wr_reg_id)&&(opa_Brd))
|
opb_B <= wr_gpreg_vl;
|
opb_B <= wr_gpreg_vl;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opa_ce)
|
if (opa_ce)
|
opa_F <= dcdF;
|
opa_F <= dcdF;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opb_ce)
|
if (opb_ce)
|
begin
|
begin
|
case(opa_F[2:0])
|
case(opa_F[2:0])
|
3'h0: r_opb_F <= 6'h00; // Always
|
3'h0: r_opb_F <= 6'h00; // Always
|
// These were remapped as part of the new instruction
|
// These were remapped as part of the new instruction
|
// set in order to make certain that the low order
|
// set in order to make certain that the low order
|
// two bits contained the most commonly used
|
// two bits contained the most commonly used
|
// conditions: Always, LT, Z, and NZ.
|
// conditions: Always, LT, Z, and NZ.
|
3'h1: r_opb_F <= 6'h24; // LT
|
3'h1: r_opb_F <= 6'h24; // LT
|
3'h2: r_opb_F <= 6'h11; // Z
|
3'h2: r_opb_F <= 6'h11; // Z
|
3'h3: r_opb_F <= 6'h10; // NE
|
3'h3: r_opb_F <= 6'h10; // NE
|
3'h4: r_opb_F <= 6'h30; // GT (!N&!Z)
|
3'h4: r_opb_F <= 6'h30; // GT (!N&!Z)
|
3'h5: r_opb_F <= 6'h20; // GE (!N)
|
3'h5: r_opb_F <= 6'h20; // GE (!N)
|
3'h6: r_opb_F <= 6'h02; // C
|
3'h6: r_opb_F <= 6'h02; // C
|
3'h7: r_opb_F <= 6'h08; // V
|
3'h7: r_opb_F <= 6'h08; // V
|
endcase
|
endcase
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
assign opb_F = { r_opb_F[3], r_opb_F[5], r_opb_F[1], r_opb_F[4:0] };
|
assign opb_F = { r_opb_F[3], r_opb_F[5], r_opb_F[1], r_opb_F[4:0] };
|
|
|
wire w_opa_valid;
|
wire w_opa_v;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
opa_valid <= 1'b0;
|
opa_v <= 1'b0;
|
else if (opa_ce)
|
else if (opa_ce)
|
opa_valid <= ((dcd_valid)||(dcd_illegal))&&(~clear_pipeline);
|
opa_v <= ((dcd_v)||(dcd_illegal))&&(~clear_pipeline);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
begin
|
begin
|
opa_valid <= 1'b0;
|
opa_v <= 1'b0;
|
end else if (opa_ce)
|
end else if (opa_ce)
|
begin
|
begin
|
opa_valid <=(dcd_valid);
|
opa_v <=(dcd_v);
|
opa_M <= (dcd_valid)&&(opa_M )&&(~opa_illegal);
|
opa_M <= (dcd_v)&&(opa_M )&&(~opa_illegal);
|
opa_DV <= (dcd_valid)&&(opa_DV )&&(~opa_illegal);
|
opa_DV <= (dcd_v)&&(opa_DV )&&(~opa_illegal);
|
opa_FP <= (dcd_valid)&&(opa_FP )&&(~opa_illegal);
|
opa_FP <= (dcd_v)&&(opa_FP )&&(~opa_illegal);
|
end else if (opb_ce)
|
end else if (opb_ce)
|
opa_valid <= 1'b0;
|
opa_v <= 1'b0;
|
|
|
initial opb_valid = 1'b0;
|
initial opb_v = 1'b0;
|
initial opb_valid_alu = 1'b0;
|
initial opb_v_alu = 1'b0;
|
initial opb_valid_mem = 1'b0;
|
initial opb_v_mem = 1'b0;
|
initial opb_valid_div = 1'b0;
|
initial opb_v_div = 1'b0;
|
initial opb_valid_fpu = 1'b0;
|
initial opb_v_fpu = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
begin
|
begin
|
opb_valid <= 1'b0;
|
opb_v <= 1'b0;
|
opb_valid_alu <= 1'b0;
|
opb_v_alu <= 1'b0;
|
opb_valid_mem <= 1'b0;
|
opb_v_mem <= 1'b0;
|
opb_valid_div <= 1'b0;
|
opb_v_div <= 1'b0;
|
opb_valid_fpu <= 1'b0;
|
opb_v_fpu <= 1'b0;
|
end else if (opb_ce)
|
end else if (opb_ce)
|
begin
|
begin
|
// Do we have a valid instruction?
|
// Do we have a valid instruction?
|
// The decoder may vote to stall one of its
|
// The decoder may vote to stall one of its
|
// instructions based upon something we currently
|
// instructions based upon something we currently
|
// have in our queue. This instruction must then
|
// have in our queue. This instruction must then
|
// move forward, and get a stall cycle inserted.
|
// move forward, and get a stall cycle inserted.
|
// Hence, the test on dcd_stalled here. If we must
|
// Hence, the test on dcd_stalled here. If we must
|
// wait until our operands are valid, then we aren't
|
// wait until our operands are valid, then we aren't
|
// valid yet until then.
|
// valid yet until then.
|
opb_valid <= (opa_valid);
|
opb_v <= (opa_v);
|
opb_valid_alu <=(opa_valid)&&((opa_ALU)||(opa_illegal));
|
opb_v_alu <=(opa_v)&&((opa_ALU)||(opa_illegal));
|
opb_valid_mem <= (opa_valid)&&(opa_M )&&(~opa_illegal);
|
opb_v_mem <= (opa_v)&&(opa_M )&&(~opa_illegal);
|
opb_valid_div <= (opa_valid)&&(opa_DV )&&(~opa_illegal);
|
opb_v_div <= (opa_v)&&(opa_DV )&&(~opa_illegal);
|
opb_valid_fpu <= (opa_valid)&&(opa_FP )&&(~opa_illegal);
|
opb_v_fpu <= (opa_v)&&(opa_FP )&&(~opa_illegal);
|
end else if ((clear_pipeline)||(stage_ce))
|
end else if ((clear_pipeline)||(stage_ce))
|
begin
|
begin
|
opb_valid <= 1'b0;
|
opb_v <= 1'b0;
|
opb_valid_alu <= 1'b0;
|
opb_v_alu <= 1'b0;
|
opb_valid_mem <= 1'b0;
|
opb_v_mem <= 1'b0;
|
opb_valid_div <= 1'b0;
|
opb_v_div <= 1'b0;
|
opb_valid_fpu <= 1'b0;
|
opb_v_fpu <= 1'b0;
|
end
|
end
|
|
|
initial op_break = 1'b0;
|
initial op_break = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst) opb_break <= 1'b0;
|
if (i_rst) opb_break <= 1'b0;
|
else if (opb_ce)
|
else if (opb_ce)
|
opb_break <= (opa_break)&&((break_en)||(~opa_gie));
|
opb_break <= (opa_break)&&((break_en)||(~opa_gie));
|
else if ((clear_pipeline)||(~opb_valid))
|
else if ((clear_pipeline)||(~opb_v))
|
opb_break <= 1'b0;
|
opb_break <= 1'b0;
|
|
|
reg r_op_lock, r_op_lock_stall;
|
reg r_op_lock, r_op_lock_stall;
|
|
|
initial r_op_lock_stall = 1'b0;
|
initial r_op_lock_stall = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_op_lock_stall <= 1'b0;
|
r_op_lock_stall <= 1'b0;
|
else
|
else
|
r_op_lock_stall <= (~opvalid)||(~op_lock)
|
r_op_lock_stall <= (~opb_v)||(~opb_lock)
|
||(~dcd_valid)||(~pf_valid);
|
||(~opa_v)||(~dcd_v)||(~pf_v);
|
|
|
assign op_lock_stall = r_op_lock_stall;
|
assign op_lock_stall = r_op_lock_stall;
|
|
|
initial opa_lock = 1'b0;
|
initial opa_lock = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
opa_lock <= 1'b0;
|
opa_lock <= 1'b0;
|
else if (opa_ce)
|
else if (opa_ce)
|
opa_lock <= (dcd_lock)&&(~clear_pipeline);
|
opa_lock <= (dcd_lock)&&(~clear_pipeline);
|
initial opb_lock = 1'b0;
|
initial opb_lock = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
opb_lock <= 1'b0;
|
opb_lock <= 1'b0;
|
else if (opb_ce)
|
else if (opb_ce)
|
opb_lock <= (opb_lock)&&(~clear_pipeline);
|
opb_lock <= (opb_lock)&&(~clear_pipeline);
|
|
|
initial opa_illegal = 1'b0;
|
initial opa_illegal = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
opa_illegal <= 1'b0;
|
opa_illegal <= 1'b0;
|
else if(opa_ce)
|
else if(opa_ce)
|
opa_illegal <=(dcd_illegal);
|
opa_illegal <=(dcd_illegal);
|
initial opb_illegal = 1'b0;
|
initial opb_illegal = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
opb_illegal <= 1'b0;
|
opb_illegal <= 1'b0;
|
else if(opb_ce)
|
else if(opb_ce)
|
opb_illegal <=(opa_illegal);
|
opb_illegal <=(opa_illegal);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opa_ce)
|
if (opa_ce)
|
begin
|
begin
|
opa_wF <= (dcdF_wr)&&((~dcdR_cc)||(~dcd_wR))
|
opa_wF <= (dcdF_wr)&&((~dcdR_cc)||(~dcd_wR))
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
opa_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
|
opa_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opb_ce)
|
if (opb_ce)
|
begin
|
begin
|
opb_wF <= opa_wF;
|
opb_wF <= opa_wF;
|
opb_wR <= opa_wR;
|
opb_wR <= opa_wR;
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opa_ce)
|
if (opa_ce)
|
begin
|
begin
|
opa_opn <= dcdOp; // Which ALU operation?
|
opa_opn <= dcdOp; // Which ALU operation?
|
opa_R <= dcd_iR;
|
opa_R <= dcd_iR;
|
opa_ccR <= (dcdR_cc)&&(dcd_wR)&&(dcd_iR[4]==dcd_gie);
|
opa_ccR <= (dcdR_cc)&&(dcd_wR)&&(dcd_iR[4]==dcd_gie);
|
opa_gie <= dcd_gie;
|
opa_gie <= dcd_gie;
|
//
|
//
|
opa_pc <= dcd_valid;
|
opa_pc <= dcd_v;
|
opa_rA <= dcd_;
|
opa_rA <= dcd_;
|
opa_rB <= dcd_;
|
opa_rB <= dcd_;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (opb_ce)
|
if (opb_ce)
|
begin
|
begin
|
opb_opn <= opa_opn;
|
opb_opn <= opa_opn;
|
opb_R <= opa_R;
|
opb_R <= opa_R;
|
opb_ccR <= opa_ccR;
|
opb_ccR <= opa_ccR;
|
opb_gie <= opa_gie;
|
opb_gie <= opa_gie;
|
//
|
//
|
opb_pc <= opa_pc;
|
opb_pc <= opa_pc;
|
end
|
end
|
assign opb_Fl = (opb_gie)?(w_uflags):(w_iflags);
|
assign opb_Fl = (opb_gie)?(w_uflags):(w_iflags);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
opa_phase <= 1'b0;
|
opa_phase <= 1'b0;
|
else if (opa_ce)
|
else if (opa_ce)
|
opa_phase <= dcd_phase;
|
opa_phase <= dcd_phase;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
opb_phase <= 1'b0;
|
opb_phase <= 1'b0;
|
else if (opb_ce)
|
else if (opb_ce)
|
opb_phase <= opa_phase;
|
opb_phase <= opa_phase;
|
|
|
assign opA = r_opA;
|
assign opA = r_opA;
|
|
|
assign dcdA_stall = (dcd_rA) // &&(dcdvalid) is checked for elsewhere
|
assign dcdA_stall = (dcd_rA) // &&(dcdvalid) is checked for elsewhere
|
&&((opa_valid)||(mem_rdbusy)
|
&&((opa_v)||(mem_rdbusy)
|
||(div_busy)||(fpu_busy))
|
||(div_busy)||(fpu_busy))
|
&&((opF_wr)&&(dcdA_cc));
|
&&((opF_wr)&&(dcdA_cc));
|
|
|
assign dcdB_stall = (dcdB_rd)
|
assign dcdB_stall = (dcdB_rd)
|
&&((opa_valid)||(mem_rdbusy)
|
&&((opa_v)||(mem_rdbusy)
|
||(div_busy)||(fpu_busy)||(alu_busy))
|
||(div_busy)||(fpu_busy)||(alu_busy))
|
&&(
|
&&(
|
// 1.
|
// 1.
|
((~dcd_zI)&&(
|
((~dcd_zI)&&(
|
((opb_R == dcdB)&&(opb_wR))
|
((opb_R == dcdB)&&(opb_wR))
|
||((mem_rdbusy)&&(~dcd_pipe))
|
||((mem_rdbusy)&&(~dcd_pipe))
|
))
|
))
|
// 2.
|
// 2.
|
||((opF_wr)&&(dcdB_cc))
|
||((opF_wr)&&(dcdB_cc))
|
);
|
);
|
assign dcdF_stall = ((~dcdF[3])
|
assign dcdF_stall = ((~dcdF[3])
|
||((dcd_rA)&&(dcdA_cc))
|
||((dcd_rA)&&(dcdA_cc))
|
||((dcd_rB)&&(dcdB_cc)))
|
||((dcd_rB)&&(dcdB_cc)))
|
&&(opvalid)&&(opb_ccR);
|
&&(opb_v)&&(opb_ccR);
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #4 :: Apply Instruction
|
// PIPELINE STAGE #4 :: Apply Instruction
|
//
|
//
|
//
|
//
|
fastops fastalu(i_clk, i_rst, alu_ce,
|
fastops fastalu(i_clk, i_rst, alu_ce,
|
(opb_valid_alu), opb_opn, opb_A, opb_B,
|
(opb_v_alu), opb_opn, opb_A, opb_B,
|
alu_result, alu_flags, alu_valid, alu_illegal_op,
|
alu_result, alu_flags, alu_v, alu_illegal_op,
|
alu_busy);
|
alu_busy);
|
|
|
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opb_opn[0],
|
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opb_opn[0],
|
opb_A, opb_B, div_busy, div_valid, div_error, div_result,
|
opb_A, opb_B, div_busy, div_v, div_error, div_result,
|
div_flags);
|
div_flags);
|
|
|
generate
|
generate
|
if (IMPLEMENT_FPU != 0)
|
if (IMPLEMENT_FPU != 0)
|
begin
|
begin
|
//
|
//
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
|
// opA, opB, fpu_busy, fpu_v, fpu_err, fpu_result,
|
// fpu_flags);
|
// fpu_flags);
|
//
|
//
|
assign fpu_error = 1'b0; // Must only be true if fpu_valid
|
assign fpu_error = 1'b0; // Must only be true if fpu_v
|
assign fpu_busy = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_v = 1'b0;
|
assign fpu_result= 32'h00;
|
assign fpu_result= 32'h00;
|
assign fpu_flags = 4'h0;
|
assign fpu_flags = 4'h0;
|
end else begin
|
end else begin
|
assign fpu_error = 1'b0;
|
assign fpu_error = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_v = 1'b0;
|
assign fpu_result= 32'h00;
|
assign fpu_result= 32'h00;
|
assign fpu_flags = 4'h0;
|
assign fpu_flags = 4'h0;
|
end endgenerate
|
end endgenerate
|
|
|
|
|
assign set_cond = ((opb_F[7:4]&opb_Fl[3:0])==opb_F[3:0]);
|
assign set_cond = ((opb_F[7:4]&opb_Fl[3:0])==opb_F[3:0]);
|
initial alF_wr = 1'b0;
|
initial alF_wr = 1'b0;
|
initial alu_wr = 1'b0;
|
initial alu_wr = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
begin
|
begin
|
alu_wr <= 1'b0;
|
alu_wr <= 1'b0;
|
alF_wr <= 1'b0;
|
alF_wr <= 1'b0;
|
end else if (alu_ce)
|
end else if (alu_ce)
|
begin
|
begin
|
// alu_reg <= opR;
|
// alu_reg <= opR;
|
alu_wr <= (opb_wR)&&(set_cond);
|
alu_wr <= (opb_wR)&&(set_cond);
|
alF_wr <= (opb_wF)&&(set_cond);
|
alF_wr <= (opb_wF)&&(set_cond);
|
end else if (~alu_busy) begin
|
end else if (~alu_busy) begin
|
// These are strobe signals, so clear them if not
|
// These are strobe signals, so clear them if not
|
// set for any particular clock
|
// set for any particular clock
|
alu_wr <= (i_halt)&&(i_dbg_we);
|
alu_wr <= (i_halt)&&(i_dbg_we);
|
alF_wr <= 1'b0;
|
alF_wr <= 1'b0;
|
end
|
end
|
|
|
initial alu_phase = 1'b0;
|
initial alu_phase = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
alu_phase <= 1'b0;
|
alu_phase <= 1'b0;
|
else if ((adf_ce_unconditional)||(mem_ce))
|
else if ((adf_ce_unconditional)||(mem_ce))
|
alu_phase <= opb_phase;
|
alu_phase <= opb_phase;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (adf_ce_unconditional)
|
if (adf_ce_unconditional)
|
alu_reg <= opb_R;
|
alu_reg <= opb_R;
|
else if ((i_halt)&&(i_dbg_we))
|
else if ((i_halt)&&(i_dbg_we))
|
alu_reg <= i_dbg_reg;
|
alu_reg <= i_dbg_reg;
|
|
|
//
|
//
|
// DEBUG Register write access starts here
|
// DEBUG Register write access starts here
|
//
|
//
|
reg dbgv;
|
reg dbgv;
|
initial dbgv = 1'b0;
|
initial dbgv = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
reg [31:0] dbg_val;
|
reg [31:0] dbg_val;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbg_val <= i_dbg_data;
|
dbg_val <= i_dbg_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (stage_ce)
|
if (stage_ce)
|
alu_gie <= op_gie;
|
alu_gie <= op_gie;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (stage_ce)
|
if (stage_ce)
|
alu_pc <= opb_pc;
|
alu_pc <= opb_pc;
|
|
|
initial alu_illegal = 0;
|
initial alu_illegal = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (clear_pipeline)
|
if (clear_pipeline)
|
alu_illegal <= 1'b0;
|
alu_illegal <= 1'b0;
|
else if (stage_ce)
|
else if (stage_ce)
|
alu_illegal <= opb_illegal;
|
alu_illegal <= opb_illegal;
|
|
|
initial r_alu_pc_valid = 1'b0;
|
initial r_alu_pc_v = 1'b0;
|
initial mem_pc_valid = 1'b0;
|
initial mem_pc_v = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_alu_pc_valid <= 1'b0;
|
r_alu_pc_v <= 1'b0;
|
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
|
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
|
r_alu_pc_valid <= 1'b1;
|
r_alu_pc_v <= 1'b1;
|
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
|
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
|
r_alu_pc_valid <= 1'b0;
|
r_alu_pc_v <= 1'b0;
|
assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
|
assign alu_pc_v = (r_alu_pc_v)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
mem_pc_valid <= 1'b0;
|
mem_pc_v <= 1'b0;
|
else
|
else
|
mem_pc_valid <= (mem_ce);
|
mem_pc_v <= (mem_ce);
|
|
|
wire bus_lock;
|
wire bus_lock;
|
|
|
reg [1:0] r_bus_lock;
|
reg [1:0] r_bus_lock;
|
initial r_bus_lock = 2'b00;
|
initial r_bus_lock = 2'b00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_bus_lock <= 2'b00;
|
r_bus_lock <= 2'b00;
|
else if ((opb_ce)&&(opb_lock))
|
else if ((opb_ce)&&(opb_lock))
|
r_bus_lock <= 2'b11;
|
r_bus_lock <= 2'b11;
|
else if ((|r_bus_lock)&&((~opb_valid_mem)||(~opb_ce)))
|
else if ((|r_bus_lock)&&((~opb_v_mem)||(~opb_ce)))
|
r_bus_lock <= r_bus_lock + 2'b11; // r_bus_lock -= 1
|
r_bus_lock <= r_bus_lock + 2'b11; // r_bus_lock -= 1
|
assign bus_lock = |r_bus_lock;
|
assign bus_lock = |r_bus_lock;
|
|
|
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
(opb_opn[0]), opb_B, opb_A, opb_R,
|
(opb_opn[0]), opb_B, opb_A, opb_R,
|
mem_busy, mem_pipe_stalled,
|
mem_busy, mem_pipe_stalled,
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_v, bus_err, mem_wreg, mem_result,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data,
|
mem_we, mem_addr, mem_data,
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
// Either the prefetch or the instruction gets the memory bus, but
|
// never both.
|
// never both.
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
// Memory access to the arbiter, priority position
|
// Memory access to the arbiter, priority position
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
|
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
|
// Prefetch access to the arbiter
|
// Prefetch access to the arbiter
|
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
|
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err,
|
pf_ack, pf_stall, pf_err,
|
// Common wires, in and out, of the arbiter
|
// Common wires, in and out, of the arbiter
|
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
|
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
|
o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_we, o_wb_addr, o_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_err);
|
i_wb_ack, i_wb_stall, i_wb_err);
|
|
|
|
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #5 :: Write-back results
|
// PIPELINE STAGE #5 :: Write-back results
|
//
|
//
|
//
|
//
|
|
|
// Unlike previous versions of the writeback routine(s), this version
|
// Unlike previous versions of the writeback routine(s), this version
|
// requires that everything be registered and clocked as soon as it is
|
// requires that everything be registered and clocked as soon as it is
|
// valid. So, let's start by clocking in our results.
|
// valid. So, let's start by clocking in our results.
|
reg [4:0] r_wr_reg;
|
reg [4:0] r_wr_reg;
|
reg [31:0] r_wr_val;
|
reg [31:0] r_wr_val;
|
reg r_wr_ce, r_wr_err;
|
reg r_wr_ce, r_wr_err;
|
|
|
// 1. Will we need to write a register?
|
// 1. Will we need to write a register?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_ce <= (dbgv)||(mem_valid)
|
r_wr_ce <= (dbgv)||(mem_v)
|
||((~clear_pipeline)&&(~alu_illegal)
|
||((~clear_pipeline)&&(~alu_illegal)
|
&&(((alu_wr)&&(alu_valid))
|
&&(((alu_wr)&&(alu_v))
|
||(div_valid)||(fpu_valid)));
|
||(div_v)||(fpu_v)));
|
assign wr_reg_ce = r_wr_ce;
|
assign wr_reg_ce = r_wr_ce;
|
|
|
// 2. Did the ALU/MEM/DIV/FPU stage produce an error of any type?
|
// 2. Did the ALU/MEM/DIV/FPU stage produce an error of any type?
|
// a. Illegal instruction
|
// a. Illegal instruction
|
// b. Division by zero
|
// b. Division by zero
|
// c. Floating point error
|
// c. Floating point error
|
// d. Bus Error
|
// d. Bus Error
|
// these will be causes for an interrupt on the next clock after this
|
// these will be causes for an interrupt on the next clock after this
|
// one.
|
// one.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_err <= ((div_valid)&&(div_error))
|
r_wr_err <= ((div_v)&&(div_error))
|
||((fpu_valid)&&(fpu_error))
|
||((fpu_v)&&(fpu_error))
|
||((alu_pc_valid)&&(alu_illegal))
|
||((alu_pc_v)&&(alu_illegal))
|
||(bus_err);
|
||(bus_err);
|
reg r_wr_illegal;
|
reg r_wr_illegal;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_illegal <= (alu_pc_valid)&&(alu_illegal);
|
r_wr_illegal <= (alu_pc_v)&&(alu_illegal);
|
|
|
// Which register shall be written?
|
// Which register shall be written?
|
// Note that the alu_reg is the register to write on a divide or
|
// Note that the alu_reg is the register to write on a divide or
|
// FPU operation.
|
// FPU operation.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_reg <= (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
r_wr_reg <= (alu_wr|div_v|fpu_v)?alu_reg:mem_wreg;
|
assign wr_reg_id = r_wr_reg;
|
assign wr_reg_id = r_wr_reg;
|
|
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
|
|
// What value to write?
|
// What value to write?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_val <= ((mem_valid) ? mem_result
|
r_wr_val <= ((mem_v) ? mem_result
|
:((div_valid|fpu_valid))
|
:((div_v|fpu_v))
|
? ((div_valid) ? div_result:fpu_result)
|
? ((div_v) ? div_result:fpu_result)
|
:((dbgv) ? dbg_val : alu_result));
|
:((dbgv) ? dbg_val : alu_result));
|
assign wr_gpreg_vl = r_wr_val;
|
assign wr_gpreg_vl = r_wr_val;
|
assign wr_spreg_vl = r_wr_val;
|
assign wr_spreg_vl = r_wr_val;
|
|
|
// Do we write back our flags?
|
// Do we write back our flags?
|
reg r_wr_flags_ce;
|
reg r_wr_flags_ce;
|
initial r_wr_flags_ce = 1'b0;
|
initial r_wr_flags_ce = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_flags_ce <= ((alF_wr)||(div_valid)||(fpu_valid))
|
r_wr_flags_ce <= ((alF_wr)||(div_v)||(fpu_v))
|
&&(~clear_pipeline)&&(~alu_illegal);
|
&&(~clear_pipeline)&&(~alu_illegal);
|
assign wr_flags_ce = r_wr_flags_ce;
|
assign wr_flags_ce = r_wr_flags_ce;
|
|
|
reg [3:0] r_wr_newflags;
|
reg [3:0] r_wr_newflags;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (div_valid)
|
if (div_v)
|
r_wr_newflags <= div_flags;
|
r_wr_newflags <= div_flags;
|
else if (fpu_valid)
|
else if (fpu_v)
|
r_wr_newflags <= fpu_flags;
|
r_wr_newflags <= fpu_flags;
|
else // if (alu_valid)
|
else // if (alu_v)
|
r_wr_newflags <= alu_flags;
|
r_wr_newflags <= alu_flags;
|
|
|
reg r_wr_gie;
|
reg r_wr_gie;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_gie <= (~dbgv)&&(alu_gie);
|
r_wr_gie <= (~dbgv)&&(alu_gie);
|
|
|
reg r_wr_pc_valid;
|
reg r_wr_pc_v;
|
initial r_wr_pc_valid = 1'b0;
|
initial r_wr_pc_v = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_pc_valid <= ((alu_pc_valid)&&(~clear_pipeline))
|
r_wr_pc_v <= ((alu_pc_v)&&(~clear_pipeline))
|
||(mem_pc_valid);
|
||(mem_pc_v);
|
reg [(AW-1):0] r_wr_pc;
|
reg [(AW-1):0] r_wr_pc;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_wr_pc <= alu_pc; // (alu_pc_valid)?alu_pc : mem_pc;
|
r_wr_pc <= alu_pc; // (alu_pc_v)?alu_pc : mem_pc;
|
|
|
////
|
////
|
//
|
//
|
//
|
//
|
// Write back, second clock
|
// Write back, second clock
|
//
|
//
|
//
|
//
|
////
|
////
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wr_reg_ce)
|
if (wr_reg_ce)
|
regset[wr_reg_id] <= wr_gpreg_vl;
|
regset[wr_reg_id] <= wr_gpreg_vl;
|
|
|
|
|
assign w_uflags = { uhalt_phase, ufpu_err_flag,
|
assign w_uflags = { uhalt_phase, ufpu_err_flag,
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
1'b0, step, 1'b1, sleep,
|
1'b0, step, 1'b1, sleep,
|
((wr_flags_ce)&&(alu_gie))?r_wr_newflags:flags };
|
((wr_flags_ce)&&(alu_gie))?r_wr_newflags:flags };
|
assign w_iflags = { ihalt_phase, ifpu_err_flag,
|
assign w_iflags = { ihalt_phase, ifpu_err_flag,
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
break_en, 1'b0, 1'b0, sleep,
|
break_en, 1'b0, 1'b0, sleep,
|
((wr_flags_ce)&&(~alu_gie))?r_wr_newflags:iflags };
|
((wr_flags_ce)&&(~alu_gie))?r_wr_newflags:iflags };
|
|
|
|
|
// What value to write?
|
// What value to write?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// If explicitly writing the register itself
|
// If explicitly writing the register itself
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
flags <= wr_gpreg_vl[3:0];
|
flags <= wr_gpreg_vl[3:0];
|
// Otherwise if we're setting the flags from an ALU operation
|
// Otherwise if we're setting the flags from an ALU operation
|
else if ((wr_flags_ce)&&(alu_gie))
|
else if ((wr_flags_ce)&&(alu_gie))
|
flags <= r_wr_newflags;
|
flags <= r_wr_newflags;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
iflags <= wr_gpreg_vl[3:0];
|
iflags <= wr_gpreg_vl[3:0];
|
else if ((wr_flags_ce)&&(~alu_gie))
|
else if ((wr_flags_ce)&&(~alu_gie))
|
iflags <= r_wr_newflags;
|
iflags <= r_wr_newflags;
|
|
|
// The 'break' enable bit. This bit can only be set from supervisor
|
// The 'break' enable bit. This bit can only be set from supervisor
|
// mode. It control what the CPU does upon encountering a break
|
// mode. It control what the CPU does upon encountering a break
|
// instruction.
|
// instruction.
|
//
|
//
|
// The goal, upon encountering a break is that the CPU should stop and
|
// The goal, upon encountering a break is that the CPU should stop and
|
// not execute the break instruction, choosing instead to enter into
|
// not execute the break instruction, choosing instead to enter into
|
// either interrupt mode or halt first.
|
// either interrupt mode or halt first.
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
// HALT CPU
|
// HALT CPU
|
// else if (break_instruction) // only in user mode
|
// else if (break_instruction) // only in user mode
|
// set an interrupt flag, set the user break bit,
|
// set an interrupt flag, set the user break bit,
|
// go to supervisor mode, allow supervisor to step the CPU.
|
// go to supervisor mode, allow supervisor to step the CPU.
|
// Upon a CPU halt, any break condition will be reset. The
|
// Upon a CPU halt, any break condition will be reset. The
|
// external debugger will then need to deal with whatever
|
// external debugger will then need to deal with whatever
|
// condition has taken place.
|
// condition has taken place.
|
initial break_en = 1'b0;
|
initial break_en = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_halt))
|
if ((i_rst)||(i_halt))
|
break_en <= 1'b0;
|
break_en <= 1'b0;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
|
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
|
|
|
reg pipe_busy;
|
reg pipe_busy;
|
initial pipe_busy <= 1'b0;
|
initial pipe_busy <= 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pipe_busy <= ((mem_ce)||(alu_ce)||(div_ce)||(fpu_ce))
|
pipe_busy <= ((mem_ce)||(alu_ce)||(div_ce)||(fpu_ce))
|
||((alu_busy)||(mem_busy)||(div_busy)||(fpu_busy));
|
||((alu_busy)||(mem_busy)||(div_busy)||(fpu_busy));
|
|
|
// pending_break <= ((break_en)||(~op_gie))&&(op_break)
|
// pending_break <= ((break_en)||(~op_gie))&&(op_break)
|
assign o_break = ((op_break)&&(~pipe_busy)&&(~clear_pipeline))
|
assign o_break = ((op_break)&&(~pipe_busy)&&(~clear_pipeline))
|
||((~r_wr_gie)&&(r_wr_err));
|
||((~r_wr_gie)&&(r_wr_err));
|
|
|
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
// The GIE register. Only interrupts can disable the interrupt register
|
reg slow_interrupt, fast_interrupt;
|
reg slow_interrupt, fast_interrupt;
|
initial slow_interrupt = 1'b0;
|
initial slow_interrupt = 1'b0;
|
// The key difference between a fast interrupt and a slow interrupt
|
// The key difference between a fast interrupt and a slow interrupt
|
// is that a fast interrupt requires the pipeline to be cleared,
|
// is that a fast interrupt requires the pipeline to be cleared,
|
// whereas a slow interrupt does not.
|
// whereas a slow interrupt does not.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
slow_interrupt <= (gie)&&(
|
slow_interrupt <= (gie)&&(
|
(i_interrupt)
|
(i_interrupt)
|
// If we encounter a break instruction, if the break
|
// If we encounter a break instruction, if the break
|
// enable isn't set. This is slow because pre
|
// enable isn't set. This is slow because pre
|
// ALU logic will prevent the break from moving forward.
|
// ALU logic will prevent the break from moving forward.
|
||((op_break)&&(~break_en)));
|
||((op_break)&&(~break_en)));
|
initial fast_interrupt = 1'b0;
|
initial fast_interrupt = 1'b0;
|
always @(posedge i_clk) // 12 inputs
|
always @(posedge i_clk) // 12 inputs
|
fast_interrupt <= ((gie)||(alu_gie))&&(
|
fast_interrupt <= ((gie)||(alu_gie))&&(
|
((r_wr_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
|
((r_wr_pc_v)&&(step)&&(~alu_phase)&&(~bus_lock))
|
// Or ... if we encountered some form of error in our
|
// Or ... if we encountered some form of error in our
|
// instruction ...
|
// instruction ...
|
||(r_wr_err)
|
||(r_wr_err)
|
// Or if we write to the CC register.
|
// Or if we write to the CC register.
|
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc)));
|
&&(wr_reg_id[4])&&(wr_write_cc)));
|
|
|
assign w_switch_to_interrupt = fast_interrupt;
|
assign w_switch_to_interrupt = fast_interrupt;
|
|
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
// Then if we write the CC register
|
// Then if we write the CC register
|
&&(((wr_reg_ce)&&(~r_wr_gie)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(((wr_reg_ce)&&(~r_wr_gie)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(~wr_reg_id[4])&&(wr_write_cc))
|
&&(~wr_reg_id[4])&&(wr_write_cc))
|
);
|
);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
gie <= 1'b0;
|
gie <= 1'b0;
|
else if ((fast_interrupt)||(slow_interrupt))
|
else if ((fast_interrupt)||(slow_interrupt))
|
gie <= 1'b0;
|
gie <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
gie <= 1'b1;
|
gie <= 1'b1;
|
|
|
initial trap = 1'b0;
|
initial trap = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
trap <= 1'b0;
|
trap <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
trap <= 1'b0;
|
trap <= 1'b0;
|
else if ((r_wr_gie)&&(wr_reg_ce)&&(wr_write_cc)
|
else if ((r_wr_gie)&&(wr_reg_ce)&&(wr_write_cc)
|
&&(~wr_spreg_vl[`CPU_GIE_BIT]))
|
&&(~wr_spreg_vl[`CPU_GIE_BIT]))
|
// &&(wr_reg_id[4]) implied
|
// &&(wr_reg_id[4]) implied
|
trap <= 1'b1;
|
trap <= 1'b1;
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
|
trap <= wr_spreg_vl[`CPU_TRAP_BIT];
|
trap <= wr_spreg_vl[`CPU_TRAP_BIT];
|
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
// The sleep register. Setting the sleep register causes the CPU to
|
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
// interrupt mode causes the processor to halt until a reset. This is
|
// interrupt mode causes the processor to halt until a reset. This is
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// set the sleep bit and switch to supervisor mode in the same
|
// set the sleep bit and switch to supervisor mode in the same
|
// instruction: users are not allowed to halt the CPU.
|
// instruction: users are not allowed to halt the CPU.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(slow_interrupt))
|
if ((i_rst)||(slow_interrupt))
|
sleep <= 1'b0;
|
sleep <= 1'b0;
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~r_wr_gie))
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~r_wr_gie))
|
// In supervisor mode, we have no protections. The
|
// In supervisor mode, we have no protections. The
|
// supervisor can set the sleep bit however he wants.
|
// supervisor can set the sleep bit however he wants.
|
// Well ... not quite. Switching to user mode and
|
// Well ... not quite. Switching to user mode and
|
// sleep mode shouold only be possible if the interrupt
|
// sleep mode shouold only be possible if the interrupt
|
// flag isn't set.
|
// flag isn't set.
|
// Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
|
// Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
|
// don't set the sleep bit
|
// don't set the sleep bit
|
// otherwise however it would o.w. be set
|
// otherwise however it would o.w. be set
|
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
|
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
|
&&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
|
&&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
|
// In user mode, however, you can only set the sleep
|
// In user mode, however, you can only set the sleep
|
// mode while remaining in user mode. You can't switch
|
// mode while remaining in user mode. You can't switch
|
// to sleep mode *and* supervisor mode at the same
|
// to sleep mode *and* supervisor mode at the same
|
// time, lest you halt the CPU.
|
// time, lest you halt the CPU.
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(fast_interrupt))
|
if ((i_rst)||(fast_interrupt))
|
step <= 1'b0;
|
step <= 1'b0;
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
|
else if (((alu_pc_v)||(mem_pc_v))&&(step)&&(gie))
|
step <= 1'b0;
|
step <= 1'b0;
|
|
|
|
|
initial ill_err_i = 1'b0;
|
initial ill_err_i = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ill_err_i <= 1'b0;
|
ill_err_i <= 1'b0;
|
// Only the debug interface can clear this bit
|
// Only the debug interface can clear this bit
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
&&(~wr_spreg_vl[`CPU_ILL_BIT]))
|
&&(~wr_spreg_vl[`CPU_ILL_BIT]))
|
ill_err_i <= 1'b0;
|
ill_err_i <= 1'b0;
|
else if ((r_wr_illegal)&&(~r_wr_gie))
|
else if ((r_wr_illegal)&&(~r_wr_gie))
|
ill_err_i <= 1'b1;
|
ill_err_i <= 1'b1;
|
initial ill_err_u = 1'b0;
|
initial ill_err_u = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// The bit is automatically cleared on release from interrupt
|
// The bit is automatically cleared on release from interrupt
|
// or reset
|
// or reset
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
ill_err_u <= 1'b0;
|
ill_err_u <= 1'b0;
|
// If the supervisor writes to this register, clearing the
|
// If the supervisor writes to this register, clearing the
|
// bit, then clear it
|
// bit, then clear it
|
else if ((~r_wr_gie)
|
else if ((~r_wr_gie)
|
&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_ILL_BIT])
|
&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_ILL_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
ill_err_u <= 1'b0;
|
ill_err_u <= 1'b0;
|
else if ((r_wr_gie)&&(r_wr_illegal))
|
else if ((r_wr_gie)&&(r_wr_illegal))
|
ill_err_u <= 1'b1;
|
ill_err_u <= 1'b1;
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
// ever set.
|
// ever set.
|
initial ibus_err_flag = 1'b0;
|
initial ibus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ibus_err_flag <= 1'b0;
|
ibus_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
&&(~wr_spreg_vl[`CPU_BUSERR_BIT]))
|
&&(~wr_spreg_vl[`CPU_BUSERR_BIT]))
|
ibus_err_flag <= 1'b0;
|
ibus_err_flag <= 1'b0;
|
else if ((bus_err)&&(~alu_gie))
|
else if ((bus_err)&&(~alu_gie))
|
ibus_err_flag <= 1'b1;
|
ibus_err_flag <= 1'b1;
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// supervisor mode.
|
// supervisor mode.
|
initial ubus_err_flag = 1'b0;
|
initial ubus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ubus_err_flag <= 1'b0;
|
ubus_err_flag <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
ubus_err_flag <= 1'b0;
|
ubus_err_flag <= 1'b0;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_spreg_vl[`CPU_BUSERR_BIT])
|
&&(~wr_spreg_vl[`CPU_BUSERR_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
ubus_err_flag <= 1'b0;
|
ubus_err_flag <= 1'b0;
|
else if ((bus_err)&&(alu_gie))
|
else if ((bus_err)&&(alu_gie))
|
ubus_err_flag <= 1'b1;
|
ubus_err_flag <= 1'b1;
|
|
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
|
|
// Supervisor/interrupt divide (by zero) error flag -- this will
|
// Supervisor/interrupt divide (by zero) error flag -- this will
|
// crash the CPU if ever set. This bit is thus available for us
|
// crash the CPU if ever set. This bit is thus available for us
|
// to be able to tell if/why the CPU crashed.
|
// to be able to tell if/why the CPU crashed.
|
initial r_idiv_err_flag = 1'b0;
|
initial r_idiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_idiv_err_flag <= 1'b0;
|
r_idiv_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
&&(~wr_spreg_vl[`CPU_DIVERR_BIT]))
|
&&(~wr_spreg_vl[`CPU_DIVERR_BIT]))
|
r_idiv_err_flag <= 1'b0;
|
r_idiv_err_flag <= 1'b0;
|
else if ((div_error)&&(div_valid)&&(~r_wr_gie))
|
else if ((div_error)&&(div_v)&&(~r_wr_gie))
|
r_idiv_err_flag <= 1'b1;
|
r_idiv_err_flag <= 1'b1;
|
// User divide (by zero) error flag -- if ever set, it will
|
// User divide (by zero) error flag -- if ever set, it will
|
// cause a sudden switch interrupt to supervisor mode.
|
// cause a sudden switch interrupt to supervisor mode.
|
initial r_udiv_err_flag = 1'b0;
|
initial r_udiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_udiv_err_flag <= 1'b0;
|
r_udiv_err_flag <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
r_udiv_err_flag <= 1'b0;
|
r_udiv_err_flag <= 1'b0;
|
else if (((~r_wr_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~r_wr_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_spreg_vl[`CPU_DIVERR_BIT])
|
&&(~wr_spreg_vl[`CPU_DIVERR_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_udiv_err_flag <= 1'b0;
|
r_udiv_err_flag <= 1'b0;
|
else if ((div_error)&&(r_wr_gie)&&(div_valid))
|
else if ((div_error)&&(r_wr_gie)&&(div_v))
|
r_udiv_err_flag <= 1'b1;
|
r_udiv_err_flag <= 1'b1;
|
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
assign idiv_err_flag = r_idiv_err_flag;
|
assign udiv_err_flag = r_udiv_err_flag;
|
assign udiv_err_flag = r_udiv_err_flag;
|
|
|
generate
|
generate
|
if (IMPLEMENT_FPU !=0)
|
if (IMPLEMENT_FPU !=0)
|
begin
|
begin
|
// Supervisor/interrupt floating point error flag -- this will
|
// Supervisor/interrupt floating point error flag -- this will
|
// crash the CPU if ever set.
|
// crash the CPU if ever set.
|
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
initial r_ifpu_err_flag = 1'b0;
|
initial r_ifpu_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_ifpu_err_flag <= 1'b0;
|
r_ifpu_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
&&(~wr_spreg_vl[`CPU_FPUERR_BIT]))
|
&&(~wr_spreg_vl[`CPU_FPUERR_BIT]))
|
r_ifpu_err_flag <= 1'b0;
|
r_ifpu_err_flag <= 1'b0;
|
else if ((fpu_error)&&(fpu_valid)&&(~r_wr_gie))
|
else if ((fpu_error)&&(fpu_v)&&(~r_wr_gie))
|
r_ifpu_err_flag <= 1'b1;
|
r_ifpu_err_flag <= 1'b1;
|
// User floating point error flag -- if ever set, it will cause
|
// User floating point error flag -- if ever set, it will cause
|
// a sudden switch interrupt to supervisor mode.
|
// a sudden switch interrupt to supervisor mode.
|
initial r_ufpu_err_flag = 1'b0;
|
initial r_ufpu_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_ufpu_err_flag <= 1'b0;
|
r_ufpu_err_flag <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
r_ufpu_err_flag <= 1'b0;
|
r_ufpu_err_flag <= 1'b0;
|
else if (((~r_wr_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~r_wr_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_spreg_vl[`CPU_FPUERR_BIT])
|
&&(~wr_spreg_vl[`CPU_FPUERR_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_ufpu_err_flag <= 1'b0;
|
r_ufpu_err_flag <= 1'b0;
|
else if ((fpu_error)&&(r_wr_gie)&&(fpu_valid))
|
else if ((fpu_error)&&(r_wr_gie)&&(fpu_v))
|
r_ufpu_err_flag <= 1'b1;
|
r_ufpu_err_flag <= 1'b1;
|
|
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
end else begin
|
end else begin
|
assign ifpu_err_flag = 1'b0;
|
assign ifpu_err_flag = 1'b0;
|
assign ufpu_err_flag = 1'b0;
|
assign ufpu_err_flag = 1'b0;
|
end endgenerate
|
end endgenerate
|
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_VLIW
|
reg r_ihalt_phase, r_uhalt_phase;
|
reg r_ihalt_phase, r_uhalt_phase;
|
|
|
initial r_ihalt_phase = 0;
|
initial r_ihalt_phase = 0;
|
initial r_uhalt_phase = 0;
|
initial r_uhalt_phase = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_ihalt_phase <= 1'b0;
|
r_ihalt_phase <= 1'b0;
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
else if ((~alu_gie)&&(alu_pc_v)&&(~clear_pipeline))
|
r_ihalt_phase <= alu_phase;
|
r_ihalt_phase <= alu_phase;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (r_wr_gie)
|
if (r_wr_gie)
|
r_uhalt_phase <= alu_phase;
|
r_uhalt_phase <= alu_phase;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
r_uhalt_phase <= 1'b0;
|
r_uhalt_phase <= 1'b0;
|
|
|
assign ihalt_phase = r_ihalt_phase;
|
assign ihalt_phase = r_ihalt_phase;
|
assign uhalt_phase = r_uhalt_phase;
|
assign uhalt_phase = r_uhalt_phase;
|
`else
|
`else
|
assign ihalt_phase = 1'b0;
|
assign ihalt_phase = 1'b0;
|
assign uhalt_phase = 1'b0;
|
assign uhalt_phase = 1'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write backs to the PC register, and general increments of it
|
// Write backs to the PC register, and general increments of it
|
// We support two: upc and ipc. If the instruction is normal,
|
// We support two: upc and ipc. If the instruction is normal,
|
// we increment upc, if interrupt level we increment ipc. If
|
// we increment upc, if interrupt level we increment ipc. If
|
// the instruction writes the PC, we write whichever PC is appropriate.
|
// the instruction writes the PC, we write whichever PC is appropriate.
|
//
|
//
|
// Do we need to all our partial results from the pipeline?
|
// Do we need to all our partial results from the pipeline?
|
// What happens when the pipeline has gie and ~gie instructions within
|
// What happens when the pipeline has gie and ~gie instructions within
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// a non-gie instruction?
|
// a non-gie instruction?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
upc <= wr_spreg_vl[(AW-1):0];
|
upc <= wr_spreg_vl[(AW-1):0];
|
else if ((r_wr_gie)&&
|
else if ((r_wr_gie)&&
|
(((alu_pc_valid)&&(~clear_pipeline))
|
(((alu_pc_v)&&(~clear_pipeline))
|
||(mem_pc_valid)))
|
||(mem_pc_v)))
|
upc <= alu_pc;
|
upc <= alu_pc;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ipc <= RESET_ADDRESS;
|
ipc <= RESET_ADDRESS;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
ipc <= wr_spreg_vl[(AW-1):0];
|
ipc <= wr_spreg_vl[(AW-1):0];
|
else if ((~r_wr_gie)&&
|
else if ((~r_wr_gie)&&
|
(((alu_pc_valid)&&(~clear_pipeline))
|
(((alu_pc_v)&&(~clear_pipeline))
|
||(mem_pc_valid)))
|
||(mem_pc_v)))
|
ipc <= alu_pc;
|
ipc <= alu_pc;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
pf_pc <= RESET_ADDRESS;
|
pf_pc <= RESET_ADDRESS;
|
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
|
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
|
pf_pc <= ipc;
|
pf_pc <= ipc;
|
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
|
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
|
pf_pc <= upc;
|
pf_pc <= upc;
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
pf_pc <= wr_spreg_vl[(AW-1):0];
|
pf_pc <= wr_spreg_vl[(AW-1):0];
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
pf_pc <= dcd_branch_pc + 1;
|
pf_pc <= dcd_branch_pc + 1;
|
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
|
else if ((new_pc)||((~dcd_stalled)&&(pf_v)))
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
`else
|
`else
|
else if ((alu_gie==gie)&&(
|
else if ((alu_gie==gie)&&(
|
((alu_pc_valid)&&(~clear_pipeline))
|
((alu_pc_v)&&(~clear_pipeline))
|
||(mem_pc_valid)))
|
||(mem_pc_v)))
|
pf_pc <= alu_pc;
|
pf_pc <= alu_pc;
|
`endif
|
`endif
|
|
|
initial new_pc = 1'b1;
|
initial new_pc = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_pf_cache))
|
if ((i_rst)||(i_clear_pf_cache))
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else
|
else
|
new_pc <= 1'b0;
|
new_pc <= 1'b0;
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
reg r_clear_icache;
|
reg r_clear_icache;
|
initial r_clear_icache = 1'b1;
|
initial r_clear_icache = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_pf_cache))
|
if ((i_rst)||(i_clear_pf_cache))
|
r_clear_icache <= 1'b1;
|
r_clear_icache <= 1'b1;
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
else
|
else
|
r_clear_icache <= 1'b0;
|
r_clear_icache <= 1'b0;
|
assign w_clear_icache = r_clear_icache;
|
assign w_clear_icache = r_clear_icache;
|
`else
|
`else
|
assign w_clear_icache = 1'b0;
|
assign w_clear_icache = 1'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// The debug interface
|
// The debug interface
|
generate
|
generate
|
if (AW<32)
|
if (AW<32)
|
begin
|
begin
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
end
|
end
|
end else begin
|
end else begin
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
end
|
end
|
end endgenerate
|
end endgenerate
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_halted <= (i_halt)&&(
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r_halted <= (i_halt)&&(
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// To be halted, any long lasting instruction must
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// To be halted, any long lasting instruction must
|
// be completed.
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// be completed.
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(~pf_cyc)&&(~mem_busy)&&(~alu_busy)
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(~pf_cyc)&&(~mem_busy)&&(~alu_busy)
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&&(~div_busy)&&(~fpu_busy)
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&&(~div_busy)&&(~fpu_busy)
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// Operations must either be valid, or illegal
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// Operations must either be valid, or illegal
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&&((opvalid)||(i_rst)||(dcd_illegal))
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&&((opb_v)||(i_rst)||(dcd_illegal))
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// Decode stage must be either valid, in reset, or ill
|
// Decode stage must be either valid, in reset, or ill
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&&((dcdvalid)||(i_rst)||(pf_illegal)));
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&&((dcdvalid)||(i_rst)||(pf_illegal)));
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assign o_dbg_stall = ~r_halted;
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assign o_dbg_stall = ~r_halted;
|
|
|
//
|
//
|
//
|
//
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// Produce accounting outputs: Account for any CPU stalls, so we can
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// later evaluate how well we are doing.
|
// later evaluate how well we are doing.
|
//
|
//
|
//
|
//
|
assign o_op_stall = (master_ce)&&(op_stall);
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assign o_op_stall = (master_ce)&&(op_stall);
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
assign o_pf_stall = (master_ce)&&(~pf_v);
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
assign o_i_count = (alu_pc_v)&&(~clear_pipeline);
|
|
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_debug <= {
|
o_debug <= {
|
/*
|
/*
|
o_break, i_wb_err, pf_pc[1:0],
|
o_break, i_wb_err, pf_pc[1:0],
|
flags,
|
flags,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
pf_v, dcdvalid, opvalid, alu_v, mem_v,
|
op_ce, alu_ce, mem_ce,
|
op_ce, alu_ce, mem_ce,
|
//
|
//
|
master_ce, opvalid_alu, opvalid_mem,
|
master_ce, opvalid_alu, opvalid_mem,
|
//
|
//
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
mem_we,
|
mem_we,
|
// ((opvalid_alu)&&(alu_stall))
|
// ((opvalid_alu)&&(alu_stall))
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// opA[23:20], opA[3:0],
|
// opA[23:20], opA[3:0],
|
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
|
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
|
*/
|
*/
|
/*
|
/*
|
i_rst, master_ce, (new_pc),
|
i_rst, master_ce, (new_pc),
|
((dcd_early_branch)&&(dcdvalid)),
|
((dcd_early_branch)&&(dcdvalid)),
|
pf_valid, pf_illegal,
|
pf_v, pf_illegal,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
pf_pc[7:0], pf_addr[7:0]
|
pf_pc[7:0], pf_addr[7:0]
|
*/
|
*/
|
|
|
i_wb_err, gie, alu_illegal,
|
i_wb_err, gie, alu_illegal,
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
mem_busy,
|
mem_busy,
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
o_wb_addr[8:0] }
|
o_wb_addr[8:0] }
|
: { instruction[31:21] },
|
: { instruction[31:21] },
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
pf_v, (pf_v) ? alu_pc[14:0]
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
|
|
/*
|
/*
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
pf_v, pf_cyc, pf_stb, instruction_pc[0], // 4
|
instruction[30:27], // 4
|
instruction[30:27], // 4
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
dcdvalid,
|
dcdvalid,
|
((dcd_early_branch)&&(~clear_pipeline)) // 15
|
((dcd_early_branch)&&(~clear_pipeline)) // 15
|
? dcd_branch_pc[14:0]:pf_pc[14:0]
|
? dcd_branch_pc[14:0]:pf_pc[14:0]
|
*/
|
*/
|
};
|
};
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
