////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: fastio.v
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// Filename: fastio.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`include "builddate.v"
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`include "builddate.v"
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//
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//
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module fastio(i_clk,
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module fastio(i_clk,
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// Board level I/O
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// Board level I/O
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i_sw, i_btn, o_led,
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i_sw, i_btn, o_led,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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// Board level PMod I/O
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// Board level PMod I/O
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i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
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i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
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// i_gpio, o_gpio,
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// i_gpio, o_gpio,
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// Wishbone control
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// Wishbone control
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
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i_wb_data, o_wb_ack, o_wb_stall, o_wb_data,
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i_wb_data, o_wb_ack, o_wb_stall, o_wb_data,
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// Cross-board I/O
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// Cross-board I/O
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i_rtc_ppd, i_buserr, i_other_ints, o_bus_int, o_board_ints);
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i_rtc_ppd, i_buserr, i_other_ints, o_bus_int, o_board_ints);
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parameter AUXUART_SETUP = 30'd1736, // 115200 baud from 200MHz clk
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parameter AUXUART_SETUP = 30'd1736, // 115200 baud from 200MHz clk
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GPSUART_SETUP = 30'd20833; // 9600 baud from 200MHz clk
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GPSUART_SETUP = 30'd20833, // 9600 baud from 200MHz clk
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EXTRACLOCK = 1; // Do we need an extra clock to process?
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input i_clk;
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input i_clk;
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// Board level I/O
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// Board level I/O
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input [3:0] i_sw;
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input [3:0] i_sw;
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input [3:0] i_btn;
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input [3:0] i_btn;
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output wire [3:0] o_led;
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output wire [3:0] o_led;
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output reg [2:0] o_clr_led0;
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output reg [2:0] o_clr_led0;
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output reg [2:0] o_clr_led1;
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output reg [2:0] o_clr_led1;
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output reg [2:0] o_clr_led2;
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output reg [2:0] o_clr_led2;
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output reg [2:0] o_clr_led3;
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output reg [2:0] o_clr_led3;
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// Board level PMod I/O
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// Board level PMod I/O
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//
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//
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// Auxilliary UART I/O
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// Auxilliary UART I/O
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input i_aux_rx;
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input i_aux_rx;
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output wire o_aux_tx, o_aux_cts;
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output wire o_aux_tx, o_aux_cts;
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//
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//
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// GPS UART I/O
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// GPS UART I/O
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input i_gps_rx;
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input i_gps_rx;
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output wire o_gps_tx;
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output wire o_gps_tx;
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//
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//
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// GPIO
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// GPIO
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// input [(NGPI-1):0] i_gpio;
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// input [(NGPI-1):0] i_gpio;
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// output reg [(NGPO-1):0] o_gpio;
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// output reg [(NGPO-1):0] o_gpio;
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//
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//
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [4:0] i_wb_addr;
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input [4:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// A strobe at midnight, to keep the calendar on "time"
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// A strobe at midnight, to keep the calendar on "time"
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input i_rtc_ppd;
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input i_rtc_ppd;
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// Address of the last bus error
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// Address of the last bus error
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input [31:0] i_buserr;
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input [31:0] i_buserr;
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//
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//
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// Interrupts -- both the output bus interrupt, as well as those
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// Interrupts -- both the output bus interrupt, as well as those
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// internally generated interrupts which may be used elsewhere
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// internally generated interrupts which may be used elsewhere
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// in the design
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// in the design
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input wire [8:0] i_other_ints;
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input wire [8:0] i_other_ints;
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output wire o_bus_int;
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output wire o_bus_int;
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output wire [5:0] o_board_ints; // Button and switch interrupts
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output wire [5:0] o_board_ints; // Button and switch interrupts
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wire [31:0] w_wb_data;
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wire [4:0] w_wb_addr;
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wire w_wb_stb;
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generate
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if (EXTRACLOCK == 0)
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begin
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assign w_wb_data = i_wb_data;
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assign w_wb_addr = i_wb_addr;
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assign w_wb_stb = (i_wb_stb)&&(i_wb_we);
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end else begin
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reg last_wb_stb;
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reg last_wb_stb;
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reg [4:0] last_wb_addr;
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reg [4:0] last_wb_addr;
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reg [31:0] last_wb_data;
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reg [31:0] last_wb_data;
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initial last_wb_stb = 1'b0;
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initial last_wb_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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last_wb_addr <= i_wb_addr;
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last_wb_addr <= i_wb_addr;
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last_wb_data <= i_wb_data;
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last_wb_data <= i_wb_data;
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last_wb_stb <= (i_wb_stb)&&(i_wb_we);
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last_wb_stb <= (i_wb_stb)&&(i_wb_we);
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end
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end
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assign w_wb_data = last_wb_data;
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assign w_wb_addr = last_wb_addr;
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assign w_wb_stb = last_wb_stb;
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end endgenerate
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wire [31:0] pic_data;
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wire [31:0] pic_data;
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reg sw_int, btn_int;
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reg sw_int, btn_int;
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wire pps_int, rtc_int, netrx_int, nettx_int,
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wire pps_int, rtc_int, netrx_int, nettx_int,
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auxrx_int, auxtx_int, gpio_int, flash_int, scop_int,
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auxrx_int, auxtx_int, gpio_int, flash_int, scop_int,
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gpsrx_int, sd_int, oled_int, zip_int;
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gpsrx_int, sd_int, oled_int, zip_int;
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assign { zip_int, oled_int, rtc_int, sd_int,
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assign { zip_int, oled_int, rtc_int, sd_int,
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nettx_int, netrx_int, scop_int, flash_int,
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nettx_int, netrx_int, scop_int, flash_int,
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pps_int } = i_other_ints;
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pps_int } = i_other_ints;
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//
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//
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// The BUS Interrupt controller
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// The BUS Interrupt controller
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//
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//
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icontrol #(15) buspic(i_clk, 1'b0,
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icontrol #(15) buspic(i_clk, 1'b0,
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(last_wb_stb)&&(last_wb_addr==5'h1),
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(w_wb_stb)&&(w_wb_addr==5'h1),
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i_wb_data, pic_data,
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i_wb_data, pic_data,
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{ zip_int, oled_int, sd_int,
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{ zip_int, oled_int, sd_int,
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gpsrx_int, scop_int, flash_int, gpio_int,
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gpsrx_int, scop_int, flash_int, gpio_int,
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auxtx_int, auxrx_int, nettx_int, netrx_int,
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auxtx_int, auxrx_int, nettx_int, netrx_int,
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rtc_int, pps_int, sw_int, btn_int },
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rtc_int, pps_int, sw_int, btn_int },
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o_bus_int);
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o_bus_int);
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//
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//
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// PWR Count
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// PWR Count
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//
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//
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// A 32-bit counter that starts at power up and never resets. It's a
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// A 32-bit counter that starts at power up and never resets. It's a
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// read only counter if you will.
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// read only counter if you will.
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reg [31:0] pwr_counter;
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reg [31:0] pwr_counter;
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initial pwr_counter = 32'h00;
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initial pwr_counter = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwr_counter <= pwr_counter+32'h001;
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pwr_counter <= pwr_counter+32'h001;
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//
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//
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// BTNSW
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// BTNSW
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//
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//
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// The button and switch control register
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// The button and switch control register
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wire [31:0] w_btnsw;
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wire [31:0] w_btnsw;
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reg [3:0] r_sw, swcfg, swnow, swlast;
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reg [3:0] r_sw, swcfg, swnow, swlast;
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reg [3:0] r_btn, btncfg, btnnow, btnlast, btnstate;
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reg [3:0] r_btn, btncfg, btnnow, btnlast, btnstate;
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initial btn_int = 1'b0;
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initial btn_int = 1'b0;
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initial sw_int = 1'b0;
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initial sw_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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r_sw <= i_sw;
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r_sw <= i_sw;
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swnow <= r_sw;
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swnow <= r_sw;
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swlast<= swnow;
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swlast<= swnow;
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sw_int <= |((swnow^swlast)|swcfg);
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sw_int <= |((swnow^swlast)|swcfg);
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if ((last_wb_stb)&&(last_wb_addr == 5'h4))
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if ((w_wb_stb)&&(w_wb_addr == 5'h4))
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swcfg <= ((last_wb_data[3:0])&(last_wb_data[11:8]))
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swcfg <= ((w_wb_data[3:0])&(w_wb_data[11:8]))
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|((~last_wb_data[3:0])&(swcfg));
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|((~w_wb_data[3:0])&(swcfg));
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r_btn <= i_btn;
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r_btn <= i_btn;
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btnnow <= r_btn;
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btnnow <= r_btn;
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btn_int <= |(btnnow&btncfg);
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btn_int <= |(btnnow&btncfg);
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if ((last_wb_stb)&&(last_wb_addr == 5'h4))
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if ((w_wb_stb)&&(w_wb_addr == 5'h4))
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begin
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begin
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btncfg <= ((last_wb_data[7:4])&(last_wb_data[15:12]))
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btncfg <= ((w_wb_data[7:4])&(w_wb_data[15:12]))
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|((~last_wb_data[7:4])&(btncfg));
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|((~w_wb_data[7:4])&(btncfg));
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btnstate<= (btnnow)|((btnstate)&(~last_wb_data[7:4]));
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btnstate<= (btnnow)|((btnstate)&(~w_wb_data[7:4]));
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end else
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end else
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btnstate <= (btnstate)|(btnnow);
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btnstate <= (btnstate)|(btnnow);
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end
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end
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assign w_btnsw = { 8'h00, btnnow, 4'h0, btncfg, swcfg, btnstate, swnow };
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assign w_btnsw = { 8'h00, btnnow, 4'h0, btncfg, swcfg, btnstate, swnow };
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//
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//
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// LEDCTRL
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// LEDCTRL
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//
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//
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reg [3:0] r_leds;
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reg [3:0] r_leds;
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wire [31:0] w_ledreg;
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wire [31:0] w_ledreg;
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reg last_cyc;
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always @(posedge i_clk)
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last_cyc <= i_wb_cyc;
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initial r_leds = 4'h0;
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initial r_leds = 4'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((last_wb_stb)&&(last_wb_addr == 5'h5))
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if ((w_wb_stb)&&(w_wb_addr == 5'h5))
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r_leds <= ((last_wb_data[7:4])&(last_wb_data[3:0]))
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r_leds <= ((w_wb_data[7:4])&(w_wb_data[3:0]))
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|((~last_wb_data[7:4])&(r_leds));
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|((~w_wb_data[7:4])&(r_leds));
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assign o_led = r_leds;
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assign o_led = r_leds;
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assign w_ledreg = { 28'h0, r_leds };
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assign w_ledreg = { 28'h0, r_leds };
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//
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//
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// GPIO
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// GPIO
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//
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//
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// Not used (yet), but this interface should allow us to control up to
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// Not used (yet), but this interface should allow us to control up to
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// 16 GPIO inputs, and another 16 GPIO outputs. The interrupt trips
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// 16 GPIO inputs, and another 16 GPIO outputs. The interrupt trips
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// when any of the inputs changes. (Sorry, which input isn't (yet)
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// when any of the inputs changes. (Sorry, which input isn't (yet)
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// selectable.)
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// selectable.)
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//
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//
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assign gpio_int = 1'b0;
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assign gpio_int = 1'b0;
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//
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//
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// AUX (UART) SETUP
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// AUX (UART) SETUP
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//
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//
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// Set us up for 4Mbaud, 8 data bits, no stop bits.
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// Set us up for 4Mbaud, 8 data bits, no stop bits.
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reg [29:0] aux_setup;
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reg [29:0] aux_setup;
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initial aux_setup = AUXUART_SETUP;
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initial aux_setup = AUXUART_SETUP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((last_wb_stb)&&(last_wb_addr == 5'h6))
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if ((w_wb_stb)&&(w_wb_addr == 5'h6))
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aux_setup[29:0] <= last_wb_data[29:0];
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aux_setup[29:0] <= w_wb_data[29:0];
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//
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//
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// GPSSETUP
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// GPSSETUP
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//
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//
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// Set us up for 9600 kbaud, 8 data bits, no stop bits.
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// Set us up for 9600 kbaud, 8 data bits, no stop bits.
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reg [29:0] gps_setup;
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reg [29:0] gps_setup;
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initial gps_setup = GPSUART_SETUP;
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initial gps_setup = GPSUART_SETUP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((last_wb_stb)&&(last_wb_addr == 5'h7))
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if ((w_wb_stb)&&(w_wb_addr == 5'h7))
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gps_setup[29:0] <= last_wb_data[29:0];
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gps_setup[29:0] <= w_wb_data[29:0];
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//
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//
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// CLR LEDs
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// CLR LEDs
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//
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//
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// CLR LED 0
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// CLR LED 0
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wire [31:0] w_clr_led0;
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wire [31:0] w_clr_led0;
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reg [8:0] r_clr_led0_r, r_clr_led0_g, r_clr_led0_b;
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reg [8:0] r_clr_led0_r, r_clr_led0_g, r_clr_led0_b;
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initial r_clr_led0_r = 9'h003; // Color LED on the far right
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initial r_clr_led0_r = 9'h003; // Color LED on the far right
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initial r_clr_led0_g = 9'h000;
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initial r_clr_led0_g = 9'h000;
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initial r_clr_led0_b = 9'h000;
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initial r_clr_led0_b = 9'h000;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((last_wb_stb)&&(last_wb_addr == 5'h8))
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if ((w_wb_stb)&&(w_wb_addr == 5'h8))
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begin
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begin
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r_clr_led0_r <= { last_wb_data[26], last_wb_data[23:16] };
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r_clr_led0_r <= { w_wb_data[26], w_wb_data[23:16] };
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r_clr_led0_g <= { last_wb_data[25], last_wb_data[15: 8] };
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r_clr_led0_g <= { w_wb_data[25], w_wb_data[15: 8] };
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r_clr_led0_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
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r_clr_led0_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
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end
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end
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assign w_clr_led0 = { 5'h0,
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assign w_clr_led0 = { 5'h0,
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r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8],
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r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8],
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r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0]
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r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0]
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};
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};
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always @(posedge i_clk)
|
always @(posedge i_clk)
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o_clr_led0 <= { (pwr_counter[8:0] < r_clr_led0_r),
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o_clr_led0 <= { (pwr_counter[8:0] < r_clr_led0_r),
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(pwr_counter[8:0] < r_clr_led0_g),
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(pwr_counter[8:0] < r_clr_led0_g),
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(pwr_counter[8:0] < r_clr_led0_b) };
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(pwr_counter[8:0] < r_clr_led0_b) };
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|
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// CLR LED 1
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// CLR LED 1
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wire [31:0] w_clr_led1;
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wire [31:0] w_clr_led1;
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reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b;
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reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b;
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initial r_clr_led1_r = 9'h007;
|
initial r_clr_led1_r = 9'h007;
|
initial r_clr_led1_g = 9'h000;
|
initial r_clr_led1_g = 9'h000;
|
initial r_clr_led1_b = 9'h000;
|
initial r_clr_led1_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h9))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h9))
|
begin
|
begin
|
r_clr_led1_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led1_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led1_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led1_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led1_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led1_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led1 = { 5'h0,
|
assign w_clr_led1 = { 5'h0,
|
r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8],
|
r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8],
|
r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0]
|
r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0]
|
};
|
};
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_clr_led1 <= { (pwr_counter[8:0] < r_clr_led1_r),
|
o_clr_led1 <= { (pwr_counter[8:0] < r_clr_led1_r),
|
(pwr_counter[8:0] < r_clr_led1_g),
|
(pwr_counter[8:0] < r_clr_led1_g),
|
(pwr_counter[8:0] < r_clr_led1_b) };
|
(pwr_counter[8:0] < r_clr_led1_b) };
|
// CLR LED 0
|
// CLR LED 0
|
wire [31:0] w_clr_led2;
|
wire [31:0] w_clr_led2;
|
reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b;
|
reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b;
|
initial r_clr_led2_r = 9'h00f;
|
initial r_clr_led2_r = 9'h00f;
|
initial r_clr_led2_g = 9'h000;
|
initial r_clr_led2_g = 9'h000;
|
initial r_clr_led2_b = 9'h000;
|
initial r_clr_led2_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'ha))
|
if ((w_wb_stb)&&(w_wb_addr == 5'ha))
|
begin
|
begin
|
r_clr_led2_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led2_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led2_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led2_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led2_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led2_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led2 = { 5'h0,
|
assign w_clr_led2 = { 5'h0,
|
r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8],
|
r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8],
|
r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0]
|
r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0]
|
};
|
};
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_clr_led2 <= { (pwr_counter[8:0] < r_clr_led2_r),
|
o_clr_led2 <= { (pwr_counter[8:0] < r_clr_led2_r),
|
(pwr_counter[8:0] < r_clr_led2_g),
|
(pwr_counter[8:0] < r_clr_led2_g),
|
(pwr_counter[8:0] < r_clr_led2_b) };
|
(pwr_counter[8:0] < r_clr_led2_b) };
|
// CLR LED 3
|
// CLR LED 3
|
wire [31:0] w_clr_led3;
|
wire [31:0] w_clr_led3;
|
reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b;
|
reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b;
|
initial r_clr_led3_r = 9'h01f; // LED is on far left
|
initial r_clr_led3_r = 9'h01f; // LED is on far left
|
initial r_clr_led3_g = 9'h000;
|
initial r_clr_led3_g = 9'h000;
|
initial r_clr_led3_b = 9'h000;
|
initial r_clr_led3_b = 9'h000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'hb))
|
if ((w_wb_stb)&&(w_wb_addr == 5'hb))
|
begin
|
begin
|
r_clr_led3_r <= { last_wb_data[26], last_wb_data[23:16] };
|
r_clr_led3_r <= { w_wb_data[26], w_wb_data[23:16] };
|
r_clr_led3_g <= { last_wb_data[25], last_wb_data[15: 8] };
|
r_clr_led3_g <= { w_wb_data[25], w_wb_data[15: 8] };
|
r_clr_led3_b <= { last_wb_data[24], last_wb_data[ 7: 0] };
|
r_clr_led3_b <= { w_wb_data[24], w_wb_data[ 7: 0] };
|
end
|
end
|
assign w_clr_led3 = { 5'h0,
|
assign w_clr_led3 = { 5'h0,
|
r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8],
|
r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8],
|
r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0]
|
r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0]
|
};
|
};
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_clr_led3 <= { (pwr_counter[8:0] < r_clr_led3_r),
|
o_clr_led3 <= { (pwr_counter[8:0] < r_clr_led3_r),
|
(pwr_counter[8:0] < r_clr_led3_g),
|
(pwr_counter[8:0] < r_clr_led3_g),
|
(pwr_counter[8:0] < r_clr_led3_b) };
|
(pwr_counter[8:0] < r_clr_led3_b) };
|
|
|
//
|
//
|
// The Calendar DATE
|
// The Calendar DATE
|
//
|
//
|
wire [31:0] date_data;
|
wire [31:0] date_data;
|
`define GET_DATE
|
`define GET_DATE
|
`ifdef GET_DATE
|
`ifdef GET_DATE
|
wire date_ack, date_stall;
|
wire date_ack, date_stall;
|
rtcdate thedate(i_clk, i_rtc_ppd,
|
rtcdate thedate(i_clk, i_rtc_ppd,
|
i_wb_cyc, last_wb_stb, (last_wb_addr==5'hc), last_wb_data,
|
i_wb_cyc, w_wb_stb, (w_wb_addr==5'hc), w_wb_data,
|
date_ack, date_stall, date_data);
|
date_ack, date_stall, date_data);
|
`else
|
`else
|
assign date_data = 32'h20160000;
|
assign date_data = 32'h20160000;
|
`endif
|
`endif
|
|
|
//////
|
//////
|
//
|
//
|
// The auxilliary UART
|
// The auxilliary UART
|
//
|
//
|
//////
|
//////
|
|
|
//
|
//
|
// First the Auxilliary UART receiver
|
// First the Auxilliary UART receiver
|
//
|
//
|
wire auxrx_stb, auxrx_break, auxrx_perr, auxrx_ferr, auxck_uart;
|
wire auxrx_stb, auxrx_break, auxrx_perr, auxrx_ferr, auxck_uart;
|
wire [7:0] rx_data_aux_port;
|
wire [7:0] rx_data_aux_port;
|
rxuart auxrx(i_clk, 1'b0, aux_setup, i_aux_rx,
|
rxuart auxrx(i_clk, 1'b0, aux_setup, i_aux_rx,
|
auxrx_stb, rx_data_aux_port, auxrx_break,
|
auxrx_stb, rx_data_aux_port, auxrx_break,
|
auxrx_perr, auxrx_ferr, auxck_uart);
|
auxrx_perr, auxrx_ferr, auxck_uart);
|
|
|
wire [31:0] auxrx_data;
|
wire [31:0] auxrx_data;
|
reg [11:0] r_auxrx_data;
|
reg [11:0] r_auxrx_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (auxrx_stb)
|
if (auxrx_stb)
|
begin
|
begin
|
r_auxrx_data[11] <= auxrx_break;
|
r_auxrx_data[11] <= auxrx_break;
|
r_auxrx_data[10] <= auxrx_ferr;
|
r_auxrx_data[10] <= auxrx_ferr;
|
r_auxrx_data[ 9] <= auxrx_perr;
|
r_auxrx_data[ 9] <= auxrx_perr;
|
r_auxrx_data[7:0]<= rx_data_aux_port;
|
r_auxrx_data[7:0]<= rx_data_aux_port;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0e))||(auxrx_stb))
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0e))||(auxrx_stb))
|
r_auxrx_data[8] <= auxrx_stb;
|
r_auxrx_data[8] <= !auxrx_stb;
|
assign o_aux_cts = auxrx_stb;
|
assign o_aux_cts = auxrx_stb;
|
assign auxrx_data = { 20'h00, r_auxrx_data };
|
assign auxrx_data = { 20'h00, r_auxrx_data };
|
assign auxrx_int = r_auxrx_data[8];
|
assign auxrx_int = r_auxrx_data[8];
|
|
|
//
|
//
|
// Then the auxilliary UART transmitter
|
// Then the auxilliary UART transmitter
|
//
|
//
|
wire auxtx_busy;
|
wire auxtx_busy;
|
reg [7:0] r_auxtx_data;
|
reg [7:0] r_auxtx_data;
|
reg r_auxtx_stb, r_auxtx_break;
|
reg r_auxtx_stb, r_auxtx_break;
|
wire [31:0] auxtx_data;
|
wire [31:0] auxtx_data;
|
txuart auxtx(i_clk, 1'b0, aux_setup,
|
txuart auxtx(i_clk, 1'b0, aux_setup,
|
r_auxtx_break, r_auxtx_stb, r_auxtx_data,
|
r_auxtx_break, r_auxtx_stb, r_auxtx_data,
|
o_aux_tx, auxtx_busy);
|
o_aux_tx, auxtx_busy);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h0f))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h0f))
|
begin
|
begin
|
r_auxtx_stb <= 1'b1;
|
r_auxtx_stb <= (!r_auxtx_break)&&(!w_wb_data[9]);
|
r_auxtx_data <= last_wb_data[7:0];
|
r_auxtx_data <= w_wb_data[7:0];
|
r_auxtx_break<= last_wb_data[9];
|
r_auxtx_break<= w_wb_data[9];
|
end else if (~auxtx_busy)
|
end else if (~auxtx_busy)
|
begin
|
begin
|
r_auxtx_stb <= 1'b0;
|
r_auxtx_stb <= 1'b0;
|
r_auxtx_data <= 8'h0;
|
r_auxtx_data <= 8'h0;
|
end
|
end
|
assign auxtx_data = { 20'h00,
|
assign auxtx_data = { 20'h00,
|
auxck_uart, o_aux_tx, r_auxtx_break, auxtx_busy,
|
auxck_uart, o_aux_tx, r_auxtx_break, auxtx_busy,
|
r_auxtx_data };
|
r_auxtx_data };
|
assign auxtx_int = ~auxtx_busy;
|
assign auxtx_int = ~auxtx_busy;
|
|
|
//////
|
//////
|
//
|
//
|
// The GPS UART
|
// The GPS UART
|
//
|
//
|
//////
|
//////
|
|
|
// First the receiver
|
// First the receiver
|
wire gpsrx_stb, gpsrx_break, gpsrx_perr, gpsrx_ferr, gpsck_uart;
|
wire gpsrx_stb, gpsrx_break, gpsrx_perr, gpsrx_ferr, gpsck_uart;
|
wire [7:0] rx_data_gps_port;
|
wire [7:0] rx_data_gps_port;
|
rxuart gpsrx(i_clk, 1'b0, gps_setup, i_gps_rx,
|
rxuart gpsrx(i_clk, 1'b0, gps_setup, i_gps_rx,
|
gpsrx_stb, rx_data_gps_port, gpsrx_break,
|
gpsrx_stb, rx_data_gps_port, gpsrx_break,
|
gpsrx_perr, gpsrx_ferr, gpsck_uart);
|
gpsrx_perr, gpsrx_ferr, gpsck_uart);
|
|
|
wire [31:0] gpsrx_data;
|
wire [31:0] gpsrx_data;
|
reg [11:0] r_gpsrx_data;
|
reg [11:0] r_gpsrx_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (gpsrx_stb)
|
if (gpsrx_stb)
|
begin
|
begin
|
r_gpsrx_data[11] <= gpsrx_break;
|
r_gpsrx_data[11] <= gpsrx_break;
|
r_gpsrx_data[10] <= gpsrx_ferr;
|
r_gpsrx_data[10] <= gpsrx_ferr;
|
r_gpsrx_data[ 9] <= gpsrx_perr;
|
r_gpsrx_data[ 9] <= gpsrx_perr;
|
r_gpsrx_data[7:0]<= rx_data_gps_port;
|
r_gpsrx_data[7:0]<= rx_data_gps_port;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h10))||(gpsrx_stb))
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h10))||(gpsrx_stb))
|
r_gpsrx_data[8] <= gpsrx_stb;
|
r_gpsrx_data[8] <= gpsrx_stb;
|
assign gpsrx_data = { 20'h00, r_gpsrx_data };
|
assign gpsrx_data = { 20'h00, r_gpsrx_data };
|
assign gpsrx_int = r_gpsrx_data[8];
|
assign gpsrx_int = r_gpsrx_data[8];
|
|
|
|
|
// Then the transmitter
|
// Then the transmitter
|
reg r_gpstx_break, r_gpstx_stb;
|
reg r_gpstx_break, r_gpstx_stb;
|
reg [7:0] r_gpstx_data;
|
reg [7:0] r_gpstx_data;
|
wire gpstx_busy;
|
wire gpstx_busy;
|
wire [31:0] gpstx_data;
|
wire [31:0] gpstx_data;
|
txuart gpstx(i_clk, 1'b0, gps_setup,
|
txuart gpstx(i_clk, 1'b0, gps_setup,
|
r_gpstx_break, r_gpstx_stb, r_gpstx_data,
|
r_gpstx_break, r_gpstx_stb, r_gpstx_data,
|
o_gps_tx, gpstx_busy);
|
o_gps_tx, gpstx_busy);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h11))
|
if ((w_wb_stb)&&(w_wb_addr == 5'h11))
|
begin
|
begin
|
r_gpstx_stb <= 1'b1;
|
r_gpstx_stb <= 1'b1;
|
r_gpstx_data <= last_wb_data[7:0];
|
r_gpstx_data <= w_wb_data[7:0];
|
r_gpstx_break<= last_wb_data[9];
|
r_gpstx_break<= w_wb_data[9];
|
end else if (~gpstx_busy)
|
end else if (~gpstx_busy)
|
begin
|
begin
|
r_gpstx_stb <= 1'b0;
|
r_gpstx_stb <= 1'b0;
|
r_gpstx_data <= 8'h0;
|
r_gpstx_data <= 8'h0;
|
end
|
end
|
assign gpstx_data = { 20'h00,
|
assign gpstx_data = { 20'h00,
|
gpsck_uart, o_gps_tx, r_gpstx_break, gpstx_busy,
|
gpsck_uart, o_gps_tx, r_gpstx_break, gpstx_busy,
|
r_gpstx_data };
|
r_gpstx_data };
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(i_wb_addr)
|
case(i_wb_addr)
|
5'h00: o_wb_data <= `DATESTAMP;
|
5'h00: o_wb_data <= `DATESTAMP;
|
5'h01: o_wb_data <= pic_data;
|
5'h01: o_wb_data <= pic_data;
|
5'h02: o_wb_data <= i_buserr;
|
5'h02: o_wb_data <= i_buserr;
|
5'h03: o_wb_data <= pwr_counter;
|
5'h03: o_wb_data <= pwr_counter;
|
5'h04: o_wb_data <= w_btnsw;
|
5'h04: o_wb_data <= w_btnsw;
|
5'h05: o_wb_data <= w_ledreg;
|
5'h05: o_wb_data <= w_ledreg;
|
5'h06: o_wb_data <= { 2'b00, aux_setup };
|
5'h06: o_wb_data <= { 2'b00, aux_setup };
|
5'h07: o_wb_data <= { 2'b00, gps_setup };
|
5'h07: o_wb_data <= { 2'b00, gps_setup };
|
5'h08: o_wb_data <= w_clr_led0;
|
5'h08: o_wb_data <= w_clr_led0;
|
5'h09: o_wb_data <= w_clr_led1;
|
5'h09: o_wb_data <= w_clr_led1;
|
5'h0a: o_wb_data <= w_clr_led2;
|
5'h0a: o_wb_data <= w_clr_led2;
|
5'h0b: o_wb_data <= w_clr_led3;
|
5'h0b: o_wb_data <= w_clr_led3;
|
5'h0c: o_wb_data <= date_data;
|
5'h0c: o_wb_data <= date_data;
|
// 5'h0d: o_wb_data <= gpio_data;
|
// 5'h0d: o_wb_data <= gpio_data;
|
5'h0e: o_wb_data <= auxrx_data;
|
5'h0e: o_wb_data <= auxrx_data;
|
5'h0f: o_wb_data <= auxtx_data;
|
5'h0f: o_wb_data <= auxtx_data;
|
5'h10: o_wb_data <= gpsrx_data;
|
5'h10: o_wb_data <= gpsrx_data;
|
5'h11: o_wb_data <= gpstx_data;
|
5'h11: o_wb_data <= gpstx_data;
|
// 5'hf: UART_SETUP
|
// 5'hf: UART_SETUP
|
// 4'h6: GPIO
|
// 4'h6: GPIO
|
// ?? : GPS-UARTRX
|
// ?? : GPS-UARTRX
|
// ?? : GPS-UARTTX
|
// ?? : GPS-UARTTX
|
default: o_wb_data <= 32'h00;
|
default: o_wb_data <= 32'h00;
|
endcase
|
endcase
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_ack <= (i_wb_stb);
|
o_wb_ack <= (i_wb_stb);
|
assign o_board_ints = { gpio_int, auxrx_int, auxtx_int, gpsrx_int, sw_int, btn_int };
|
assign o_board_ints = { gpio_int, auxrx_int, auxtx_int, gpsrx_int, sw_int, btn_int };
|
|
|
|
|
endmodule
|
endmodule
|
|
|
