| Line 60... |
Line 60... |
// `define UART_ACCESS
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// `define UART_ACCESS
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// `define GPS_UART
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// `define GPS_UART
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`define RTC_ACCESS
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`define RTC_ACCESS
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`define OLEDRGB_ACCESS
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`define OLEDRGB_ACCESS
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//
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//
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`ifdef FLASH_ACCESS
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`define FLASH_SCOPE // Position zero
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`define FLASH_SCOPE // Position zero
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`else
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`ifdef ZIPCPU
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// `define CPU_SCOPE // Position zero
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// `define CPU_SCOPE // Position zero
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`endif
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`endif
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// `define GPS_SCOPE // Position one
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// `define GPS_SCOPE // Position one
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`ifdef ICAPE_ACCESS
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`define CFG_SCOPE // Position one
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`endif
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`ifdef SDRAM_ACCESS
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// `define SDRAM_SCOPE // Position two
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// `define SDRAM_SCOPE // Position two
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`endif
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// `define ENET_SCOPE
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// `define ENET_SCOPE
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//
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//
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//
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//
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module fastmaster(i_clk, i_rst,
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module fastmaster(i_clk, i_rst,
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// CNC
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// CNC
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| Line 375... |
Line 385... |
rtc_ack, sdcard_ack,
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rtc_ack, sdcard_ack,
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netp_ack, gps_ack, mio_ack, cfg_ack, netb_ack,
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netp_ack, gps_ack, mio_ack, cfg_ack, netb_ack,
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mem_ack, flash_ack, ram_ack;
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mem_ack, flash_ack, ram_ack;
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reg many_ack, slow_many_ack;
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reg many_ack, slow_many_ack;
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reg slow_ack, scop_ack;
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reg slow_ack, scop_ack;
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wire [4:0] ack_list;
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wire [5:0] ack_list;
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assign ack_list = { ram_ack, flash_ack, mem_ack, netb_ack, cfg_ack };
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assign ack_list = { ram_ack, flash_ack, mem_ack, netb_ack, netp_ack, slow_ack };
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initial many_ack = 1'b0;
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initial many_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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many_ack <= ((ack_list != 5'h10)
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many_ack <= ((ack_list != 6'h20)
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&&(ack_list != 5'h8)
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&&(ack_list != 6'h10)
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&&(ack_list != 5'h4)
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&&(ack_list != 6'h8)
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&&(ack_list != 5'h2)
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&&(ack_list != 6'h4)
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&&(ack_list != 5'h1)
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&&(ack_list != 6'h2)
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&&(ack_list != 5'h0));
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&&(ack_list != 6'h1)
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&&(ack_list != 6'h0));
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/*
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/*
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assign many_ack = ( { 2'h0, ram_ack}
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assign many_ack = ( { 2'h0, ram_ack}
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+{2'h0, flash_ack }
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+{2'h0, flash_ack }
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+{2'h0, mem_ack }
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+{2'h0, mem_ack }
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+{2'h0, netb_ack }
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+{2'h0, netb_ack }
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+{2'h0, slow_ack } > 3'h1 );
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+{2'h0, slow_ack } > 3'h1 );
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*/
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*/
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wire [7:0] slow_ack_list;
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wire [7:0] slow_ack_list;
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assign slow_ack_list = { mio_ack, gps_ack, netp_ack,
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assign slow_ack_list = { cfg_ack, mio_ack, gps_ack,
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sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
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sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
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initial slow_many_ack = 1'b0;
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initial slow_many_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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slow_many_ack <= ((slow_ack_list != 8'h80)
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slow_many_ack <= ((slow_ack_list != 8'h80)
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&&(slow_ack_list != 8'h40)
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&&(slow_ack_list != 8'h40)
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| Line 409... |
Line 420... |
&&(slow_ack_list != 8'h02)
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&&(slow_ack_list != 8'h02)
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&&(slow_ack_list != 8'h01)
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&&(slow_ack_list != 8'h01)
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&&(slow_ack_list != 8'h00));
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&&(slow_ack_list != 8'h00));
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always @(posedge i_clk)
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always @(posedge i_clk)
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wb_ack <= (wb_cyc)&&(|{ ram_ack, flash_ack, mem_ack,
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wb_ack <= (wb_cyc)&&(|ack_list);
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netb_ack, cfg_ack, slow_ack });
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always @(posedge i_clk)
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always @(posedge i_clk)
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slow_ack <= (wb_cyc)&&(|{oled_ack, mio_ack, gps_ack,
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slow_ack <= (wb_cyc)&&(|slow_ack_list);
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netp_ack, sdcard_ack, rtc_ack, scop_ack,
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oled_ack, io_ack});
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//
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//
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// Peripheral data lines
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// Peripheral data lines
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//
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//
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wire [31:0] io_data, oled_data,
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wire [31:0] io_data, oled_data,
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| Line 432... |
Line 440... |
if ((ram_ack)||(flash_ack))
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if ((ram_ack)||(flash_ack))
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wb_idata <= (ram_ack)?ram_data:flash_data;
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wb_idata <= (ram_ack)?ram_data:flash_data;
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else if ((mem_ack)||(netb_ack))
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else if ((mem_ack)||(netb_ack))
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wb_idata <= (mem_ack)?mem_data:netb_data;
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wb_idata <= (mem_ack)?mem_data:netb_data;
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else
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else
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wb_idata <= slow_data;
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wb_idata <= (netp_ack)?netp_data: slow_data;
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// 7 control lines, 8x32 data lines
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// 7 control lines, 8x32 data lines
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((cfg_ack)||(mio_ack))
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if ((cfg_ack)||(mio_ack))
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slow_data <= (cfg_ack) ? cfg_data : mio_data;
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slow_data <= (cfg_ack) ? cfg_data : mio_data;
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else if ((gps_ack)||(netp_ack))
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slow_data <= (gps_ack) ? gps_data : netp_data;
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else if ((sdcard_ack)||(rtc_ack))
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else if ((sdcard_ack)||(rtc_ack))
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slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
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slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
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else if ((scop_ack)|(oled_ack))
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else if ((scop_ack)|(oled_ack))
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slow_data <= (scop_ack)?scop_data:oled_data;
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slow_data <= (scop_ack)?scop_data:oled_data;
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else
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else
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slow_data <= io_data;
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slow_data <= (gps_ack) ? gps_data : io_data;
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//
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//
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// Peripheral stall lines
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// Peripheral stall lines
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//
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//
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// As per the wishbone spec, these cannot be clocked or delayed. They
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// As per the wishbone spec, these cannot be clocked or delayed. They
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| Line 465... |
Line 471... |
||((scop_sel)&&(scop_stall)) // Never stalls
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||((scop_sel)&&(scop_stall)) // Never stalls
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||((rtc_sel)&&(rtc_stall)) // Never stalls
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||((rtc_sel)&&(rtc_stall)) // Never stalls
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||((sdcard_sel)&&(sdcard_stall))// Never stalls
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||((sdcard_sel)&&(sdcard_stall))// Never stalls
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||((netp_sel)&&(netp_stall))
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||((netp_sel)&&(netp_stall))
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||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
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||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
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||((oled_sel)&&(oled_stall))
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||((oled_sel)&&(oled_stall)) // Never stalls
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||((mio_sel)&&(mio_stall))
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||((mio_sel)&&(mio_stall))
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||((cfg_sel)&&(cfg_stall))
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||((cfg_sel)&&(cfg_stall))
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||((netb_sel)&&(netb_stall)) // Never stalls
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||((netb_sel)&&(netb_stall)) // Never stalls
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||((mem_sel)&&(mem_stall)) // Never stalls
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||((mem_sel)&&(mem_stall)) // Never stalls
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||((flash_sel|flctl_sel)&&(flash_stall))
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||((flash_sel|flctl_sel)&&(flash_stall))
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| Line 845... |
Line 851... |
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//
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//
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// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
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// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
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//
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//
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`ifdef ICAPE_ACCESS
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`ifdef ICAPE_ACCESS
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wire [31:0] cfg_debug;
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wbicapetwo fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
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wbicapetwo fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
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wb_addr[4:0], wb_data,
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wb_addr[4:0], wb_data,
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cfg_ack, cfg_stall, cfg_data);
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cfg_ack, cfg_stall, cfg_data, cfg_debug);
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`else
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`else
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reg r_cfg_ack;
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reg r_cfg_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_cfg_ack <= (cfg_sel)&&(wb_stb);
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r_cfg_ack <= (cfg_sel)&&(wb_stb);
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assign cfg_ack = r_cfg_ack;
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assign cfg_ack = r_cfg_ack;
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| Line 1016... |
Line 1023... |
// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_gps_ack, scop_gps_stall, scop_gps_data,
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scop_gps_ack, scop_gps_stall, scop_gps_data,
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scop_gps_interrupt);
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scop_gps_interrupt);
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assign scop_b_ack = scop_gps_ack;
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assign scop_b_stall = scop_gps_stall;
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assign scop_b_data = scop_gps_data;
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assign scop_b_interrupt = scop_gps_interrupt;
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`else
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`ifdef CFG_SCOPE
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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wire [31:0] cfg_debug_2;
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assign cfg_debug_2 = {
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wb_ack, cfg_debug[30:17], slow_ack,
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slow_data[7:0], wb_data[7:0]
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};
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wbscope #(5'd8,32,1) cfgscope(i_clk, 1'b1, (cfg_sel)&&(wb_stb),
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cfg_debug_2,
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// Wishbone interface
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_interrupt);
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assign scop_b_data = scop_cfg_data;
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assign scop_b_stall = scop_cfg_stall;
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assign scop_b_ack = scop_cfg_ack;
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assign scop_b_interrupt = scop_cfg_interrupt;
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`else
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`else
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assign scop_b_data = 32'h00;
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assign scop_b_data = 32'h00;
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assign scop_b_stall = 1'b0;
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assign scop_b_stall = 1'b0;
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assign scop_b_interrupt = 1'b0;
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assign scop_b_interrupt = 1'b0;
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reg r_scop_b_ack;
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reg r_scop_b_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
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r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
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assign scop_b_ack = r_scop_b_ack;
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assign scop_b_ack = r_scop_b_ack;
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`endif
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`endif
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`endif
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//
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//
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// SCOPE C
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// SCOPE C
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//
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//
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wire [31:0] scop_c_data;
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wire [31:0] scop_c_data;
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| Line 1086... |
Line 1120... |
always @(posedge i_clk)
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always @(posedge i_clk)
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r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
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r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
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assign scop_d_ack = r_scop_d_ack;
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assign scop_d_ack = r_scop_d_ack;
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//`endif
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//`endif
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|
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assign scop_int = scop_a_interrupt
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reg all_scope_interrupts;
|
|| scop_b_interrupt
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always @(posedge i_clk)
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|| scop_c_interrupt
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all_scope_interrupts <= (scop_a_interrupt)
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|| scop_d_interrupt;
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|| (scop_b_interrupt)
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|| (scop_c_interrupt)
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|| (scop_d_interrupt);
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assign scop_int = all_scope_interrupts;
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|
|
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// Scopes don't stall, so this line is more formality than anything
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// else.
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assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
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assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
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: ((wb_addr[2:1]==2'b01)?scop_b_stall
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: ((wb_addr[2:1]==2'b01)?scop_b_stall
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: ((wb_addr[2:1]==2'b11)?scop_c_stall
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: ((wb_addr[2:1]==2'b11)?scop_c_stall
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: scop_d_stall))); // Will always be 1'b0;
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: scop_d_stall))); // Will always be 1'b0;
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initial scop_ack = 1'b0;
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initial scop_ack = 1'b0;
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