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`endif

        //

        // Proposed QSPI mode select, to allow dual I/O mode

        //      000     Normal SPI mode

        //      001     Dual mode input

        //      010     Dual mode, output

        //      101     Quad I/O mode input

        //      110     Quad I/O mode output

        //

        //

        // assign io_qspi_dat[3:2] = (~qspi_bmod[2]) ? 2'b11

        //                      : (qspi_bmod[0])?2'bzz : qspi_dat[3:2];

        // assign io_qspi_dat[1] = (~qspi_bmod[1])?qspi_dat[1]:1'bz;

        // assign io_qspi_dat[0] = (qspi_bmod[0])?1'bz : qspi_dat[0];

        //

        //

        // The following primitive is necessary on other boards in order to

        // gain access to the o_qspi_sck pin.  On the Arty, however, there is

        // a clock PIN, so we don't need this primitive.

        //

        //

/*

        wire    [3:0]   su_nc;  // Startup primitive, no connect

        STARTUPE2 #(

                // Leave PROG_USR false to avoid activating the program

                // event security feature.  Notes state that such a feature

                // requires encrypted bitstreams.

                .PROG_USR("FALSE"),

                // Sets the configuration clock frequency (in ns) for

                // simulation.

                .SIM_CCLK_FREQ(0.0)

        ) STARTUPE2_inst (

        // CFGCLK, 1'b output: Configuration main clock output -- no connect

        .CFGCLK(su_nc[0]),

        // CFGMCLK, 1'b output: Configuration internal oscillator clock output

        .CFGMCLK(su_nc[1]),

        // EOS, 1'b output: Active high output indicating the End Of Startup.

        .EOS(su_nc[2]),

        // PREQ, 1'b output: PROGRAM request to fabric output

        //      Only enabled if PROG_USR is set.  This lets the fabric know

        //      that a request has been made (either JTAG or pin pulled low)

        //      to program the device

        .PREQ(su_nc[3]),

        // CLK, 1'b input: User start-up clock input

        .CLK(1'b0),

        // GSR, 1'b input: Global Set/Reset input

        .GSR(1'b0),

        // GTS, 1'b input: Global 3-state input

        .GTS(1'b0),

        // KEYCLEARB, 1'b input: Clear AES Decrypter Key input from BBRAM

        .KEYCLEARB(1'b0),

        // PACK, 1-bit input: PROGRAM acknowledge input

        //      This pin is only enabled if PROG_USR is set.  This allows the

        //      FPGA to acknowledge a request for reprogram to allow the FPGA

        //      to get itself into a reprogrammable state first.

        .PACK(1'b0),

        // USRCLKO, 1-bit input: User CCLK input -- This is why I am using this

        // module at all.

        .USRCCLKO(qspi_sck),

        // USRCCLKTS, 1'b input: User CCLK 3-state enable input

        //      An active high here places the clock into a high impedence

        //      state.  Since we wish to use the clock as an active output

        //      always, we drive this pin low.

        .USRCCLKTS(1'b0),

        // USRDONEO, 1'b input: User DONE pin output control

        //      Set this to "high" to make sure that the DONE LED pin is

        //      high.

        .USRDONEO(1'b1),

        // USRDONETS, 1'b input: User DONE 3-state enable output

        //      This enables the FPGA DONE pin to be active.  Setting this

        //      active high sets the DONE pin to high impedence, setting it

        //      low allows the output of this pin to be as stated above.

        .USRDONETS(1'b1)

        );

*/