////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: fasttop.v
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// Filename: fasttop.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: This is the top level Verilog file. It is so named as fasttop,
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// Purpose: This is the top level Verilog file. It is so named as fasttop,
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// because my purpose will be to run the Arty at 200MHz, just to
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// because my purpose will be to run the Arty at 200MHz, just to
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// prove that I can get it up to that frequency.
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// prove that I can get it up to that frequency.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module fasttop(i_clk_100mhz, i_reset_btn,
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module fasttop(i_clk_100mhz, i_reset_btn,
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i_sw, // Switches
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i_sw, // Switches
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i_btn, // Buttons
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i_btn, // Buttons
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o_led, // Single color LEDs
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o_led, // Single color LEDs
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
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// RS232 UART
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// RS232 UART
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i_uart_rx, o_uart_tx,
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i_uart_rx, o_uart_tx,
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// Quad-SPI Flash control
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// Quad-SPI Flash control
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o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
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// Missing: Ethernet
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// Missing: Ethernet
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o_eth_mdclk, io_eth_mdio,
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o_eth_mdclk, io_eth_mdio,
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// Memory
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// Memory
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o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
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o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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io_ddr_dqs_p, io_ddr_dqs_n,
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io_ddr_dqs_p, io_ddr_dqs_n,
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o_ddr_addr, o_ddr_ba,
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o_ddr_addr, o_ddr_ba,
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io_ddr_data, o_ddr_dm, o_ddr_odt,
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io_ddr_data, o_ddr_dm, o_ddr_odt,
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// SD Card
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// SD Card
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o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
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o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
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// GPS Pmod
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// GPS Pmod
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i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
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i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
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// OLED Pmod
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// OLED Pmod
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
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o_oled_vccen, o_oled_pmoden,
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o_oled_vccen, o_oled_pmoden,
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// PMod I/O
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// PMod I/O
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i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
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i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
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);
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);
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input i_clk_100mhz, i_reset_btn;
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input i_clk_100mhz, i_reset_btn;
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input [3:0] i_sw; // Switches
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input [3:0] i_sw; // Switches
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input [3:0] i_btn; // Buttons
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input [3:0] i_btn; // Buttons
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output wire [3:0] o_led; // LED
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output wire [3:0] o_led; // LED
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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// UARTs
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// UARTs
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input i_uart_rx;
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input i_uart_rx;
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output wire o_uart_tx;
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output wire o_uart_tx;
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// Quad SPI flash
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// Quad SPI flash
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output wire o_qspi_sck, o_qspi_cs_n;
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output wire o_qspi_sck, o_qspi_cs_n;
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inout [3:0] io_qspi_dat;
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inout [3:0] io_qspi_dat;
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// Ethernet // Not yet implemented
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// Ethernet // Not yet implemented
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// Ethernet control (MDIO)
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// Ethernet control (MDIO)
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output wire o_eth_mdclk;
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output wire o_eth_mdclk;
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inout wire io_eth_mdio;
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inout wire io_eth_mdio;
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// DDR3 SDRAM
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// DDR3 SDRAM
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output wire o_ddr_reset_n;
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output wire o_ddr_reset_n;
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output wire o_ddr_cke;
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output wire o_ddr_cke;
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output wire o_ddr_ck_p, o_ddr_ck_n;
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output wire o_ddr_ck_p, o_ddr_ck_n;
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
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inout [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
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inout [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
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output wire [13:0] o_ddr_addr;
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output wire [13:0] o_ddr_addr;
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output wire [2:0] o_ddr_ba;
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output wire [2:0] o_ddr_ba;
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inout [15:0] io_ddr_data;
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inout [15:0] io_ddr_data;
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//
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//
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output wire [1:0] o_ddr_dm;
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output wire [1:0] o_ddr_dm;
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output wire o_ddr_odt;
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output wire o_ddr_odt;
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// SD Card
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// SD Card
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output wire o_sd_sck;
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output wire o_sd_sck;
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inout io_sd_cmd;
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inout io_sd_cmd;
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inout [3:0] io_sd;
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inout [3:0] io_sd;
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input i_sd_cs;
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input i_sd_cs;
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input i_sd_wp;
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input i_sd_wp;
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// GPS PMod
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// GPS PMod
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input i_gps_pps, i_gps_3df, i_gps_rx;
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input i_gps_pps, i_gps_3df, i_gps_rx;
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output wire o_gps_tx;
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output wire o_gps_tx;
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// OLEDRGB PMod
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// OLEDRGB PMod
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_pmoden;
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o_oled_pmoden;
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// Aux UART
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// Aux UART
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input i_aux_rx, i_aux_rts;
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input i_aux_rx, i_aux_rts;
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output wire o_aux_tx, o_aux_cts;
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output wire o_aux_tx, o_aux_cts;
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`define FULLCLOCK
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`define FULLCLOCK
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// Build our master clock
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// Build our master clock
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wire i_clk, clk_for_ddr, mem_serial_clk, mem_serial_clk_inv,
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wire s_clk_pll, s_clk, clk_for_ddr, mem_serial_clk, mem_serial_clk_inv,
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enet_clk, clk_halfspeed, clk_feedback, clk_locked, clk_unused;
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enet_clk, clk_halfspeed, clk_feedback, clk_locked, clk_unused;
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PLLE2_BASE #(
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PLLE2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_PHASE(0.0), // Phase off. in deg of CLKFB,(-360-360)
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
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.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
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`ifdef FULLCLOCK
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE:
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// divide amount for each CLKOUT(1-128)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(4), // 200 MHz
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.CLKOUT1_DIVIDE(1), // 800 MHz clock for DDR memory
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.CLKOUT2_DIVIDE(1), // 800 MHz clock to run DDR I/O
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.CLKOUT3_DIVIDE(1), // 800MHz clk inv to run DDR I/O
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.CLKOUT4_DIVIDE(8), // 100 MHz
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.CLKOUT5_DIVIDE(32), // 25 MHz
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`else
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// 100*64/40 = 160 -- the fastest speed where the UART will
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// still work at 4MBaud. Others will still support 115200
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// Baud
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// 100*64/36 = 177.78
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// 100*64/34 = 188.24
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// 100*64/33 = 193.94
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(5), // 160 MHz
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.CLKOUT0_DIVIDE(5), // 160 MHz
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.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
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.CLKOUT1_DIVIDE(10), // 80 MHz (Unused)
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.CLKOUT2_DIVIDE(5), // 160 MHz // Clock too slow for DDR
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.CLKOUT2_DIVIDE(16), // 50 MHz (Unused)
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.CLKOUT3_DIVIDE(5), // 160 MHz // Clock too slow for DDR
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.CLKOUT3_DIVIDE(32), // 25 MHz (Unused/Ethernet clock)
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.CLKOUT4_DIVIDE(20), // 40 MHz
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.CLKOUT4_DIVIDE(16), // 50 MHz (Unused clock?)
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.CLKOUT5_DIVIDE(5),
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.CLKOUT5_DIVIDE(24),
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`endif
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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.CLKOUT0_PHASE(0.0),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(270.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(180.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
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.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
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.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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) genclock(
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) genclock(
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// Clock outputs: 1-bit (each) output
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// Clock outputs: 1-bit (each) output
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.CLKOUT0(i_clk),
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.CLKOUT0(s_clk_pll),
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.CLKOUT1(clk_for_ddr),
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.CLKOUT1(mem_clk),
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.CLKOUT2(mem_serial_clk),
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.CLKOUT2(clk2_unused),
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.CLKOUT3(mem_serial_clk_inv),
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.CLKOUT3(enet_clk),
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.CLKOUT4(clk_unused),
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.CLKOUT4(clk4_unused),
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.CLKOUT5(enet_clk),
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.CLKOUT5(clk5_unused),
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.LOCKED(clk_locked),
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.LOCKED(clk_locked),
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.CLKIN1(i_clk_100mhz),
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.CLKIN1(i_clk_100mhz),
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.PWRDWN(1'b0),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.RST(1'b0),
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.CLKFBIN(clk_feedback) // 1-bit input, feedback clock
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.CLKFBIN(clk_feedback_bufd) // 1-bit input, feedback clock
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);
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);
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// Help reduce skew ...
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BUFG sys_clk_buffer( .I(s_clk_pll), .O(s_clk));
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BUFG feedback_buffer(.I(clk_feedback),.O(clk_feedback_bufd));
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// UART interface
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// UART interface
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wire [29:0] bus_uart_setup;
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wire [29:0] bus_uart_setup;
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`ifdef FULLCLOCK
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assign bus_uart_setup = 30'h10000028; // 4MBaud, 7 bits
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assign bus_uart_setup = 30'h10000032; // 4MBaud, 7 bits
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`else
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assign bus_uart_setup = 30'h10000028;//4MBaud,7 bits,@160MHzClk
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//assign bus_uart_setup = 30'h10000019;//4MBaud,7 bits,@100MHzClk
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`endif
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wire [7:0] rx_data, tx_data;
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wire [7:0] rx_data, tx_data;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire tx_stb, tx_busy;
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wire tx_stb, tx_busy;
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//
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//
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// RESET LOGIC
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// RESET LOGIC
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//
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//
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// Okay, so this looks bad at a first read--but it's not really that
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// Okay, so this looks bad at a first read--but it's not really that
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// bad. If you look close, there are two parts to the reset logic.
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// bad. If you look close, there are two parts to the reset logic.
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// The first is the "PRE"-reset. This is a wire, set from the external
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// The first is the "PRE"-reset. This is a wire, set from the external
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// reset button. In good old-fashioned asynch-logic to synchronous
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// reset button. In good old-fashioned asynch-logic to synchronous
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// logic fashion, we synchronize this wire by registering it first
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// logic fashion, we synchronize this wire by registering it first
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// to pre_reset, and then to pwr_reset (the actual reset wire).
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// to pre_reset, and then to pwr_reset (the actual reset wire).
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//
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//
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reg pwr_reset, pre_reset;
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reg pwr_reset, pre_reset;
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//
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//
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// Logic description starts with the PRE-reset, so as to make certain
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// Logic description starts with the PRE-reset, so as to make certain
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// we include the reset button
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// we include the reset button
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initial pre_reset = 1'b0;
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initial pre_reset = 1'b0;
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always @(posedge i_clk)
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always @(posedge s_clk)
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pre_reset <= ~i_reset_btn;
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pre_reset <= ~i_reset_btn;
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//
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//
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// and then continues with the actual reset, now that we've
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// and then continues with the actual reset, now that we've
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// synchronized our reset button wire.
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// synchronized our reset button wire.
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge s_clk)
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pwr_reset <= pre_reset;
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pwr_reset <= pre_reset;
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wire w_ck_uart, w_uart_tx;
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wire w_ck_uart, w_uart_tx;
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rxuart rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
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rxuart rcv(s_clk, pwr_reset, bus_uart_setup, i_uart_rx,
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rx_stb, rx_data, rx_break,
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rx_stb, rx_data, rx_break,
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rx_parity_err, rx_frame_err, w_ck_uart);
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rx_parity_err, rx_frame_err, w_ck_uart);
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txuart txv(i_clk, pwr_reset, bus_uart_setup, 1'b0,
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txuart txv(s_clk, pwr_reset, bus_uart_setup, 1'b0,
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tx_stb, tx_data, o_uart_tx, tx_busy);
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tx_stb, tx_data, o_uart_tx, tx_busy);
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`ifdef SDRAM_ACCESS
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`ifdef SDRAM_ACCESS
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///
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///
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///
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///
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/// The following lines are included from ddr3insert.v.
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/// The following lines are included from ddr3insert.v.
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///
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///
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wire w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe;
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wire w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe;
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wire [26:0] w_ddr_cmd_a, w_ddr_cmd_b;
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wire [26:0] w_ddr_cmd_a, w_ddr_cmd_b;
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wire [63:0] wi_ddr_data, wo_ddr_data;
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wire [63:0] wi_ddr_data, wo_ddr_data;
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wire [127:0] wide_ddr_data;
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wire [127:0] wide_ddr_data;
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//
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//
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//
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//
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// Wires for setting up the DDR3 memory
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// Wires for setting up the DDR3 memory
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//
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//
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//
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//
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// First, let's set up the clock(s)
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// First, let's set up the clock(s)
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xoddrserdesb ddrclk(mem_serial_clk, i_clk, pwr_reset, 8'h66,
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xoddrserdesb ddrclk(mem_serial_clk, i_clk, pwr_reset, 8'h66,
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o_ddr_ck_p, o_ddr_ck_n);
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o_ddr_ck_p, o_ddr_ck_n);
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wire [7:0] w_udqs_in, w_ldqs_in;
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wire [7:0] w_udqs_in, w_ldqs_in;
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xioddrserdesb ddrudqs(mem_serial_clk, mem_serial_clk_inv, i_clk,
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xioddrserdesb ddrudqs(mem_serial_clk, mem_serial_clk_inv, i_clk,
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~w_ddr_reset_n, w_ddr_cmd_a[0],
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~w_ddr_reset_n, w_ddr_cmd_a[0],
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(w_ddr_cmd_b[0])? 8'h66 : 8'h06,
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(w_ddr_cmd_b[0])? 8'h66 : 8'h06,
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w_udqs_in,
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w_udqs_in,
|
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
|
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
|
|
|
xioddrserdesb ddrldqs(mem_serial_clk, mem_serial_clk_inv, i_clk,
|
xioddrserdesb ddrldqs(mem_serial_clk, mem_serial_clk_inv, i_clk,
|
~w_ddr_reset_n, w_ddr_cmd_a[0],
|
~w_ddr_reset_n, w_ddr_cmd_a[0],
|
(w_ddr_cmd_b[0])? 8'h66 : 8'h06,
|
(w_ddr_cmd_b[0])? 8'h66 : 8'h06,
|
w_ldqs_in,
|
w_ldqs_in,
|
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
|
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
|
|
|
// The command wires: CS_N, RAS_N, CAS_N, and WE_N
|
// The command wires: CS_N, RAS_N, CAS_N, and WE_N
|
xoddrserdes ddrcsn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrcsn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[26], w_ddr_cmd_a[26],
|
{ w_ddr_cmd_a[26], w_ddr_cmd_a[26],
|
w_ddr_cmd_a[26], w_ddr_cmd_a[26],
|
w_ddr_cmd_a[26], w_ddr_cmd_a[26],
|
w_ddr_cmd_b[26], w_ddr_cmd_b[26],
|
w_ddr_cmd_b[26], w_ddr_cmd_b[26],
|
w_ddr_cmd_b[26], w_ddr_cmd_b[26] }, o_ddr_cs_n);
|
w_ddr_cmd_b[26], w_ddr_cmd_b[26] }, o_ddr_cs_n);
|
|
|
xoddrserdes ddrrasn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrrasn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[25], w_ddr_cmd_a[25],
|
{ w_ddr_cmd_a[25], w_ddr_cmd_a[25],
|
w_ddr_cmd_a[25], w_ddr_cmd_a[25],
|
w_ddr_cmd_a[25], w_ddr_cmd_a[25],
|
w_ddr_cmd_b[25], w_ddr_cmd_b[25],
|
w_ddr_cmd_b[25], w_ddr_cmd_b[25],
|
w_ddr_cmd_b[25], w_ddr_cmd_b[25] }, o_ddr_ras_n);
|
w_ddr_cmd_b[25], w_ddr_cmd_b[25] }, o_ddr_ras_n);
|
|
|
xoddrserdes ddrcasn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrcasn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[24], w_ddr_cmd_a[24],
|
{ w_ddr_cmd_a[24], w_ddr_cmd_a[24],
|
w_ddr_cmd_a[24], w_ddr_cmd_a[24],
|
w_ddr_cmd_a[24], w_ddr_cmd_a[24],
|
w_ddr_cmd_b[24], w_ddr_cmd_b[24],
|
w_ddr_cmd_b[24], w_ddr_cmd_b[24],
|
w_ddr_cmd_b[24], w_ddr_cmd_b[24] }, o_ddr_cas_n);
|
w_ddr_cmd_b[24], w_ddr_cmd_b[24] }, o_ddr_cas_n);
|
|
|
xoddrserdes ddrwen(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrwen(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[23], w_ddr_cmd_a[23],
|
{ w_ddr_cmd_a[23], w_ddr_cmd_a[23],
|
w_ddr_cmd_a[23], w_ddr_cmd_a[23],
|
w_ddr_cmd_a[23], w_ddr_cmd_a[23],
|
w_ddr_cmd_b[23], w_ddr_cmd_b[23],
|
w_ddr_cmd_b[23], w_ddr_cmd_b[23],
|
w_ddr_cmd_b[23], w_ddr_cmd_b[23] }, o_ddr_we_n);
|
w_ddr_cmd_b[23], w_ddr_cmd_b[23] }, o_ddr_we_n);
|
|
|
// Data mask wires, first the upper byte
|
// Data mask wires, first the upper byte
|
xoddrserdes ddrudm(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrudm(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[4], w_ddr_cmd_a[4],
|
{ w_ddr_cmd_a[4], w_ddr_cmd_a[4],
|
w_ddr_cmd_a[2], w_ddr_cmd_a[2],
|
w_ddr_cmd_a[2], w_ddr_cmd_a[2],
|
w_ddr_cmd_b[4], w_ddr_cmd_b[4],
|
w_ddr_cmd_b[4], w_ddr_cmd_b[4],
|
w_ddr_cmd_b[2], w_ddr_cmd_b[2] }, o_ddr_dm[1]);
|
w_ddr_cmd_b[2], w_ddr_cmd_b[2] }, o_ddr_dm[1]);
|
// then the lower byte
|
// then the lower byte
|
xoddrserdes ddrldm(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrldm(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[3], w_ddr_cmd_a[3],
|
{ w_ddr_cmd_a[3], w_ddr_cmd_a[3],
|
w_ddr_cmd_a[1], w_ddr_cmd_a[1],
|
w_ddr_cmd_a[1], w_ddr_cmd_a[1],
|
w_ddr_cmd_b[3], w_ddr_cmd_b[3],
|
w_ddr_cmd_b[3], w_ddr_cmd_b[3],
|
w_ddr_cmd_b[1], w_ddr_cmd_b[1] }, o_ddr_dm[0]);
|
w_ddr_cmd_b[1], w_ddr_cmd_b[1] }, o_ddr_dm[0]);
|
|
|
// and the On-Die termination wire
|
// and the On-Die termination wire
|
xoddrserdes ddrodt(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrodt(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[0], w_ddr_cmd_a[0],
|
{ w_ddr_cmd_a[0], w_ddr_cmd_a[0],
|
w_ddr_cmd_a[0], w_ddr_cmd_a[0],
|
w_ddr_cmd_a[0], w_ddr_cmd_a[0],
|
w_ddr_cmd_b[0], w_ddr_cmd_b[0],
|
w_ddr_cmd_b[0], w_ddr_cmd_b[0],
|
w_ddr_cmd_b[0], w_ddr_cmd_b[0] }, o_ddr_odt);
|
w_ddr_cmd_b[0], w_ddr_cmd_b[0] }, o_ddr_odt);
|
|
|
//
|
//
|
// Now for the data, bank, and address wires
|
// Now for the data, bank, and address wires
|
//
|
//
|
genvar k;
|
genvar k;
|
generate begin
|
generate begin
|
//
|
//
|
for(k=0; k<16; k=k+1)
|
for(k=0; k<16; k=k+1)
|
xioddrserdes ddrdata(mem_serial_clk, mem_serial_clk_inv, i_clk, ~w_ddr_reset_n,
|
xioddrserdes ddrdata(mem_serial_clk, mem_serial_clk_inv, i_clk, ~w_ddr_reset_n,
|
w_ddr_bus_oe,
|
w_ddr_bus_oe,
|
{ wo_ddr_data[48+k], wo_ddr_data[48+k],
|
{ wo_ddr_data[48+k], wo_ddr_data[48+k],
|
wo_ddr_data[32+k], wo_ddr_data[32+k],
|
wo_ddr_data[32+k], wo_ddr_data[32+k],
|
wo_ddr_data[16+k], wo_ddr_data[16+k],
|
wo_ddr_data[16+k], wo_ddr_data[16+k],
|
wo_ddr_data[ k], wo_ddr_data[ k] },
|
wo_ddr_data[ k], wo_ddr_data[ k] },
|
{ wide_ddr_data[112+k], wide_ddr_data[96+k],
|
{ wide_ddr_data[112+k], wide_ddr_data[96+k],
|
wide_ddr_data[ 80+k], wide_ddr_data[64+k],
|
wide_ddr_data[ 80+k], wide_ddr_data[64+k],
|
wide_ddr_data[ 48+k], wide_ddr_data[32+k],
|
wide_ddr_data[ 48+k], wide_ddr_data[32+k],
|
wide_ddr_data[ 16+k], wide_ddr_data[ k] },
|
wide_ddr_data[ 16+k], wide_ddr_data[ k] },
|
io_ddr_data[k]);
|
io_ddr_data[k]);
|
//
|
//
|
for(k=0; k<3; k=k+1)
|
for(k=0; k<3; k=k+1)
|
xoddrserdes ddrbank(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddrbank(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[20+k], w_ddr_cmd_a[20+k],
|
{ w_ddr_cmd_a[20+k], w_ddr_cmd_a[20+k],
|
w_ddr_cmd_a[20+k], w_ddr_cmd_a[20+k],
|
w_ddr_cmd_a[20+k], w_ddr_cmd_a[20+k],
|
w_ddr_cmd_b[20+k], w_ddr_cmd_b[20+k],
|
w_ddr_cmd_b[20+k], w_ddr_cmd_b[20+k],
|
w_ddr_cmd_b[20+k], w_ddr_cmd_b[20+k] },
|
w_ddr_cmd_b[20+k], w_ddr_cmd_b[20+k] },
|
o_ddr_ba[k]);
|
o_ddr_ba[k]);
|
//
|
//
|
for(k=0; k<14; k=k+1)
|
for(k=0; k<14; k=k+1)
|
xoddrserdes ddraddr(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
xoddrserdes ddraddr(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
{ w_ddr_cmd_a[ 6+k], w_ddr_cmd_a[ 6+k],
|
{ w_ddr_cmd_a[ 6+k], w_ddr_cmd_a[ 6+k],
|
w_ddr_cmd_a[ 6+k], w_ddr_cmd_a[ 6+k],
|
w_ddr_cmd_a[ 6+k], w_ddr_cmd_a[ 6+k],
|
w_ddr_cmd_b[ 6+k], w_ddr_cmd_b[ 6+k],
|
w_ddr_cmd_b[ 6+k], w_ddr_cmd_b[ 6+k],
|
w_ddr_cmd_b[ 6+k], w_ddr_cmd_b[ 6+k] },
|
w_ddr_cmd_b[ 6+k], w_ddr_cmd_b[ 6+k] },
|
o_ddr_addr[k]);
|
o_ddr_addr[k]);
|
//
|
//
|
|
|
for(k=0; k<64; k=k+1)
|
for(k=0; k<64; k=k+1)
|
assign wi_ddr_data[k] = (w_ddr_bus_oe) ? wide_ddr_data[2*k+1]
|
assign wi_ddr_data[k] = (w_ddr_bus_oe) ? wide_ddr_data[2*k+1]
|
: wide_ddr_data[2*k];
|
: wide_ddr_data[2*k];
|
end endgenerate
|
end endgenerate
|
|
|
assign o_ddr_reset_n = w_ddr_reset_n;
|
assign o_ddr_reset_n = w_ddr_reset_n;
|
assign o_ddr_cke = w_ddr_cke;
|
assign o_ddr_cke = w_ddr_cke;
|
|
|
|
|
///
|
///
|
///
|
///
|
///
|
///
|
///
|
///
|
`else
|
`else
|
wire w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe;
|
wire w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe;
|
wire [26:0] w_ddr_cmd_a, w_ddr_cmd_b;
|
wire [26:0] w_ddr_cmd_a, w_ddr_cmd_b;
|
wire [63:0] wi_ddr_data, wo_ddr_data;
|
wire [63:0] wi_ddr_data, wo_ddr_data;
|
wire [127:0] wide_ddr_data;
|
wire [127:0] wide_ddr_data;
|
|
|
//
|
//
|
//
|
//
|
// Wires for setting up the DDR3 memory
|
// Wires for setting up the DDR3 memory
|
//
|
//
|
//
|
//
|
|
|
// Leave the SDRAM in a permanent state of reset
|
// Leave the SDRAM in a permanent state of reset
|
assign o_ddr_reset_n = 1'b0;
|
assign o_ddr_reset_n = 1'b0;
|
// Leave the SDRAM clock ... disabled
|
// Leave the SDRAM clock ... disabled
|
assign o_ddr_cke = 1'b0;
|
assign o_ddr_cke = 1'b0;
|
|
|
// Disable the clock(s)
|
// Disable the clock(s)
|
OBUFDS(.I(1'b0), .O(o_ddr_ck_p), .OB(o_ddr_ck_n));
|
OBUFDS(.I(1'b0), .O(o_ddr_ck_p), .OB(o_ddr_ck_n));
|
// And the data strobe
|
// And the data strobe
|
OBUFDS(.I(1'b0), .O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]));
|
OBUFDS(.I(1'b0), .O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]));
|
OBUFDS(.I(1'b0), .O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]));
|
OBUFDS(.I(1'b0), .O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]));
|
|
|
// Output ... something, anything, on the address lines
|
// Output ... something, anything, on the address lines
|
assign o_ddr_cs_n = 1'b1; // Never enable any commands
|
assign o_ddr_cs_n = 1'b1; // Never enable any commands
|
assign o_ddr_ras_n = 1'b0;
|
assign o_ddr_ras_n = 1'b0;
|
assign o_ddr_cas_n = 1'b0;
|
assign o_ddr_cas_n = 1'b0;
|
assign o_ddr_we_n = 1'b0;
|
assign o_ddr_we_n = 1'b0;
|
assign o_ddr_ba = 3'h0;
|
assign o_ddr_ba = 3'h0;
|
assign o_ddr_addr = 14'h0;
|
assign o_ddr_addr = 14'h0;
|
assign o_ddr_dm = 2'b00;
|
assign o_ddr_dm = 2'b00;
|
assign o_ddr_odt = 1'b0;
|
assign o_ddr_odt = 1'b0;
|
|
|
assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
|
assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
|
assign wi_ddr_data = io_ddr_data;
|
assign wi_ddr_data = io_ddr_data;
|
|
|
`endif
|
`endif
|
|
|
|
|
//////
|
//////
|
//
|
//
|
//
|
//
|
// The WB bus interconnect, herein called fastmaster, which handles
|
// The WB bus interconnect, herein called fastmaster, which handles
|
// just about ... everything.
|
// just about ... everything.
|
//
|
//
|
//
|
//
|
//////
|
//////
|
wire w_qspi_sck, w_qspi_cs_n;
|
wire w_qspi_sck, w_qspi_cs_n;
|
wire [1:0] qspi_bmod;
|
wire [1:0] qspi_bmod;
|
wire [3:0] qspi_dat;
|
wire [3:0] qspi_dat;
|
wire [3:0] i_qspi_dat;
|
wire [3:0] i_qspi_dat;
|
|
|
//
|
//
|
|
wire [2:0] w_ddr_dqs;
|
|
wire [31:0] wo_ddr_data, wi_ddr_data;
|
|
//
|
wire w_mdio, w_mdwe;
|
wire w_mdio, w_mdwe;
|
//
|
//
|
wire w_sd_cmd;
|
wire w_sd_cmd;
|
wire [3:0] w_sd_data;
|
wire [3:0] w_sd_data;
|
fastmaster wbbus(i_clk, pwr_reset,
|
fastmaster wbbus(s_clk, pwr_reset,
|
// External USB-UART bus control
|
// External USB-UART bus control
|
rx_stb, rx_data, tx_stb, tx_data, tx_busy,
|
rx_stb, rx_data, tx_stb, tx_data, tx_busy,
|
// Board lights and switches
|
// Board lights and switches
|
i_sw, i_btn, o_led,
|
i_sw, i_btn, o_led,
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
// Board level PMod I/O
|
// Board level PMod I/O
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
// Quad SPI flash
|
// Quad SPI flash
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
// DDR3 SDRAM
|
// DDR3 SDRAM
|
w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe,
|
w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe,
|
w_ddr_cmd_a, w_ddr_cmd_b, wo_ddr_data, wi_ddr_data,
|
w_ddr_cmd_a, w_ddr_cmd_b, wo_ddr_data, wi_ddr_data,
|
// SD Card
|
// SD Card
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
// OLEDRGB PMod wires
|
// OLEDRGB PMod wires
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
// GPS PMod
|
// GPS PMod
|
i_gps_pps, i_gps_3df
|
i_gps_pps, i_gps_3df
|
);
|
);
|
|
|
//////
|
//////
|
//
|
//
|
//
|
//
|
// Some wires need special treatment, and so are not quite completely
|
// Some wires need special treatment, and so are not quite completely
|
// handled by the bus master. These are handled below.
|
// handled by the bus master. These are handled below.
|
//
|
//
|
//
|
//
|
//////
|
//////
|
|
|
//
|
//
|
//
|
//
|
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
|
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
|
// 0? Normal serial mode, one bit in one bit out
|
// 0? Normal serial mode, one bit in one bit out
|
// 10 Quad SPI mode, going out
|
// 10 Quad SPI mode, going out
|
// 11 Quad SPI mode coming from the device (read mode)
|
// 11 Quad SPI mode coming from the device (read mode)
|
//
|
//
|
// ?? Dual mode in (not yet)
|
// ?? Dual mode in (not yet)
|
// ?? Dual mode out (not yet)
|
// ?? Dual mode out (not yet)
|
//
|
//
|
//
|
//
|
// `define QSPI_OUT_VERSION_ONE
|
|
`ifdef QSPI_OUT_VERSION_ONE
|
|
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
|
|
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
|
|
assign i_qspi_dat = io_qspi_dat;
|
|
assign o_qspi_sck = w_qspi_sck;
|
|
`else
|
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
|
|
xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_csn( i_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
xoddr xqspi_csn( i_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
//
|
//
|
xioddr xqspi_d0( i_clk, (qspi_bmod != 2'b11),
|
xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11),
|
{ qspi_dat[0], qspi_dat[0] },
|
{ qspi_dat[0], qspi_dat[0] },
|
{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
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{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
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xioddr xqspi_d1( i_clk, (qspi_bmod==2'b10),
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xioddr xqspi_d1( s_clk, (qspi_bmod==2'b10),
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{ qspi_dat[1], qspi_dat[1] },
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{ qspi_dat[1], qspi_dat[1] },
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{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
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{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
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xioddr xqspi_d2( i_clk, (qspi_bmod!=2'b11),
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xioddr xqspi_d2( s_clk, (qspi_bmod!=2'b11),
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(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
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(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
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{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
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{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
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xioddr xqspi_d3( i_clk, (qspi_bmod!=2'b11),
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xioddr xqspi_d3( s_clk, (qspi_bmod!=2'b11),
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(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
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(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
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{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
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{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
|
|
|
assign i_qspi_dat = i_qspi_pedge;
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assign i_qspi_dat = i_qspi_pedge;
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`endif
|
//
|
|
// Proposed QSPI mode select, to allow dual I/O mode
|
|
// 000 Normal SPI mode
|
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// 001 Dual mode input
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// 010 Dual mode, output
|
|
// 101 Quad I/O mode input
|
|
// 110 Quad I/O mode output
|
|
//
|
|
//
|
|
|
|
|
//
|
//
|
//
|
//
|
// Wires for setting up the SD Card Controller
|
// Wires for setting up the SD Card Controller
|
//
|
//
|
//
|
//
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
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assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
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assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
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assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
|
assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
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assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
|
assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
|
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
|
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
|
|
|
|
|
//
|
//
|
//
|
//
|
// Wire(s) for setting up the MDIO ethernet control structure
|
// Wire(s) for setting up the MDIO ethernet control structure
|
//
|
//
|
//
|
//
|
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
|
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
|
|
|
//
|
//
|
//
|
//
|
// Wires for setting up the DDR3 memory
|
// Wires for setting up the DDR3 memory
|
//
|
//
|
//
|
//
|
|
|
/*
|
/*
|
wire w_clk_for_ddr;
|
wire w_clk_for_ddr;
|
ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
|
ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
|
memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
|
memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
|
.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
|
.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
|
OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
|
OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
|
clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
|
clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
|
*/
|
*/
|
|
|
endmodule
|
endmodule
|
|
|
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|
