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https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [gpsclock.v] - Diff between revs 3 and 12
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| Rev 3 |
Rev 12 |
| Line 181... |
Line 181... |
initial r_def_step = 32'h8_2af_31dc;
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initial r_def_step = 32'h8_2af_31dc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pre_step <= { 16'h00,
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pre_step <= { 16'h00,
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(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
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(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
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// Delay writes by one clock
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wire [1:0] wb_addr;
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wire [31:0] wb_data;
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reg wb_write;
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reg [1:0] r_wb_addr;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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wb_write <= (i_wb_cyc_stb)&&(i_wb_we);
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always @(posedge i_clk)
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r_wb_data <= i_wb_data;
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always @(posedge i_clk)
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r_wb_addr <= i_wb_addr;
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assign wb_data = r_wb_data;
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assign wb_addr = r_wb_addr;
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initial new_config = 1'b0;
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initial new_config = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc_stb)&&(i_wb_we))
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if (wb_write)
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begin
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begin
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new_config = 1'b1;
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new_config = 1'b1;
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case(i_wb_addr)
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case(wb_addr)
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2'b00: r_alpha <= i_wb_data[5:0];
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2'b00: r_alpha <= wb_data[5:0];
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2'b01: r_beta <= i_wb_data;
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2'b01: r_beta <= wb_data;
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2'b10: r_gamma <= i_wb_data;
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2'b10: r_gamma <= wb_data;
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2'b11: r_def_step <= i_wb_data;
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2'b11: r_def_step <= wb_data;
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default: begin end
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default: begin end
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// r_defstep <= i_wb_data;
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// r_defstep <= i_wb_data;
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endcase
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endcase
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end else
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end else
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new_config = 1'b0;
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new_config = 1'b0;
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