| Line 100... |
Line 100... |
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
module gpsclock(i_clk, i_rst, i_pps, o_pps, o_led,
|
module gpsclock(i_clk, i_rst, i_pps, o_pps, o_led,
|
i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
|
i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_tracking, o_count, o_step, o_err, o_locked, o_dbg);
|
o_tracking, o_count, o_step, o_err, o_locked, o_dbg);
|
|
parameter DEFAULT_STEP = 32'h834d_c736;//2^64/81.25 MHz
|
parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency))
|
parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency))
|
DW=32, // The width of our data bus
|
DW=32, // The width of our data bus
|
ONE_SECOND = 0,
|
ONE_SECOND = 0,
|
NPW=RW-DW, // Width of non-parameter data
|
NPW=RW-DW, // Width of non-parameter data
|
HRW=RW/2; // Half of RW
|
HRW=RW/2; // Half of RW
|
| Line 175... |
Line 176... |
//
|
//
|
// Wishbone access ... adjust our tracking parameters
|
// Wishbone access ... adjust our tracking parameters
|
//
|
//
|
//
|
//
|
//
|
//
|
// DEFAULT_STEP = 64'h0000_002a_f31d_c461, // 2^64 / 100 MHz
|
// DEFAULT_STEP = 64'h0000_0034_dc73_67da, // 2^64 / 100 MHz
|
initial r_def_step = 32'h8_2af_31dc;
|
// 28'h34d_c736 << 8, and hence we have 32'h834d_c736
|
|
initial r_def_step = DEFAULT_STEP;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pre_step <= { 16'h00,
|
pre_step <= { 16'h00,
|
(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
|
(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
|
|
|
// Delay writes by one clock
|
// Delay writes by one clock
|
| Line 206... |
Line 208... |
case(wb_addr)
|
case(wb_addr)
|
2'b00: r_alpha <= wb_data[5:0];
|
2'b00: r_alpha <= wb_data[5:0];
|
2'b01: r_beta <= wb_data;
|
2'b01: r_beta <= wb_data;
|
2'b10: r_gamma <= wb_data;
|
2'b10: r_gamma <= wb_data;
|
2'b11: r_def_step <= wb_data;
|
2'b11: r_def_step <= wb_data;
|
default: begin end
|
// default: begin end
|
// r_defstep <= i_wb_data;
|
// r_defstep <= i_wb_data;
|
endcase
|
endcase
|
end else
|
end else
|
new_config = 1'b0;
|
new_config = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case (i_wb_addr)
|
case (i_wb_addr)
|
2'b00: o_wb_data <= { 26'h00, r_alpha };
|
2'b00: o_wb_data <= { 26'h00, r_alpha };
|
2'b01: o_wb_data <= r_beta;
|
2'b01: o_wb_data <= r_beta;
|
2'b10: o_wb_data <= r_gamma;
|
2'b10: o_wb_data <= r_gamma;
|
2'b11: o_wb_data <= r_def_step;
|
2'b11: o_wb_data <= r_def_step;
|
default: o_wb_data <= 0;
|
// default: o_wb_data <= 0;
|
endcase
|
endcase
|
|
|
reg dly_config;
|
reg dly_config;
|
initial dly_config = 1'b0;
|
initial dly_config = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
