////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: gpsclock_tb.v
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// Filename: gpsclock_tb.v
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//
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//
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// Project: A GPS Schooled Clock Core
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// Project: A GPS Schooled Clock Core
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//
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//
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// Purpose: Provide a test bench, internal to an FPGA, whereby the GPS
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// Purpose: Provide a test bench, internal to an FPGA, whereby the GPS
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// clock module can be tested.
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// clock module can be tested.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module gpsclock_tb(i_clk, i_lcl_pps, o_pps,
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module gpsclock_tb(i_clk, i_lcl_pps, o_pps,
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i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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i_err, i_count, i_step);
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i_err, i_count, i_step);
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parameter DW=32, RW=64;
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parameter DW=32, RW=64;
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input i_clk, i_lcl_pps;
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input i_clk, i_lcl_pps;
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output reg o_pps; // To our local circuitry
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output reg o_pps; // To our local circuitry
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// Wishbone Configuration interface
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// Wishbone Configuration interface
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input i_wb_cyc_stb, i_wb_we;
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input i_wb_cyc_stb, i_wb_we;
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input [2:0] i_wb_addr;
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input [2:0] i_wb_addr;
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input [(DW-1):0] i_wb_data;
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input [(DW-1):0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [(DW-1):0] o_wb_data;
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output reg [(DW-1):0] o_wb_data;
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// Status and timing outputs
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// Status and timing outputs
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input [(RW-1):0] i_err, // Fraction of a second err
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input [(RW-1):0] i_err, // Fraction of a second err
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i_count, // Fraction of a second
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i_count, // Fraction of a second
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i_step; // 2^RW / clock speed (in Hz)
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i_step; // 2^RW / clock speed (in Hz)
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reg [31:0] r_jump, r_maxcount;
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reg [31:0] r_jump, r_maxcount;
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reg r_halt;
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reg r_halt;
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//
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//
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//
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//
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//
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//
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// Wishbone access ...
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// Wishbone access ...
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//
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//
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//
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//
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc_stb)&&(i_wb_we))
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if ((i_wb_cyc_stb)&&(i_wb_we))
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begin
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begin
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case(i_wb_addr)
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case(i_wb_addr)
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3'b000: r_maxcount <= i_wb_data;
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3'b000: r_maxcount <= i_wb_data;
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3'b001: r_jump <= i_wb_data;
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3'b001: r_jump <= i_wb_data;
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// 2'b11: r_def_step <= i_wb_data;
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// 2'b11: r_def_step <= i_wb_data;
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default: begin end
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default: begin end
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// r_defstep <= i_wb_data;
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// r_defstep <= i_wb_data;
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endcase
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endcase
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end else
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end else
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r_jump <= 32'h00;
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r_jump <= 32'h00;
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reg [31:0] r_err, r_lcl;
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reg [31:0] r_err, r_lcl;
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reg [63:0] r_count, r_step;
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reg [63:0] r_count, r_step;
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initial r_lcl = 32'h000;
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initial r_lcl = 32'h000;
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initial r_halt = 1'b0;
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initial r_halt = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case (i_wb_addr)
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case (i_wb_addr)
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3'b000: o_wb_data <= r_maxcount;
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3'b000: o_wb_data <= r_maxcount;
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3'b001: begin o_wb_data <= r_lcl; r_halt <= 1'b1; end // { 31'h00, r_halt };
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3'b001: begin o_wb_data <= r_lcl; r_halt <= 1'b1; end // { 31'h00, r_halt };
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3'b010: begin o_wb_data <= i_err[63:32]; r_halt <= 1'b1; end
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3'b010: begin o_wb_data <= i_err[63:32]; r_halt <= 1'b1; end
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3'b011: o_wb_data <= r_err[31:0];
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3'b011: o_wb_data <= r_err[31:0];
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3'b100: o_wb_data <= r_count[63:32];
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3'b100: o_wb_data <= r_count[63:32];
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3'b101: o_wb_data <= r_count[31:0];
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3'b101: o_wb_data <= r_count[31:0];
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3'b110: o_wb_data <= r_step[63:32];
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3'b110: o_wb_data <= r_step[63:32];
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3'b111: begin o_wb_data <= r_step[31:0]; r_halt <= 1'b0; end
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3'b111: begin o_wb_data <= r_step[31:0]; r_halt <= 1'b0; end
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default: o_wb_data <= 0;
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// default: o_wb_data <= 0;
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endcase
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endcase
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= i_wb_cyc_stb;
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o_wb_ack <= i_wb_cyc_stb;
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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//
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//
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//
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//
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// Generate a PPS signal
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// Generate a PPS signal
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//
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//
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//
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//
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reg [31:0] r_ctr;
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reg [31:0] r_ctr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (r_ctr >= r_maxcount-1)
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if (r_ctr >= r_maxcount-1)
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r_ctr <= r_ctr+1-r_maxcount+r_jump;
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r_ctr <= r_ctr+1-r_maxcount+r_jump;
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else
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else
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r_ctr <= r_ctr+1+r_jump;
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r_ctr <= r_ctr+1+r_jump;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (r_ctr >= r_maxcount-1)
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if (r_ctr >= r_maxcount-1)
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o_pps <= 1'b1;
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o_pps <= 1'b1;
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else
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else
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o_pps <= 1'b0;
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o_pps <= 1'b0;
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reg [31:0] lcl_counter;
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reg [31:0] lcl_counter;
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always @(posedge i_clk)
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always @(posedge i_clk)
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lcl_counter <= lcl_counter + 32'h001;
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lcl_counter <= lcl_counter + 32'h001;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~r_halt)&&(i_lcl_pps))
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if ((~r_halt)&&(i_lcl_pps))
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begin
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begin
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r_err <= i_err[31:0];
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r_err <= i_err[31:0];
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r_count <= i_count;
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r_count <= i_count;
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r_step <= i_step;
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r_step <= i_step;
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r_lcl <= lcl_counter;
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r_lcl <= lcl_counter;
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end
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end
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endmodule
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endmodule
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