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https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [lleqspi.v] - Diff between revs 3 and 12
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| Rev 3 |
Rev 12 |
| Line 295... |
Line 295... |
o_dat <= 4'hd;
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o_dat <= 4'hd;
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end
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end
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*/
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*/
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end
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end
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`define EXTRA_DELAY
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`ifdef EXTRA_DELAY
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reg rd_input_2, rd_valid_2, r_spd_2;
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always @(posedge i_clk)
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rd_input_2 <= rd_input;
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always @(posedge i_clk)
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rd_valid_2 <= rd_valid;
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always @(posedge i_clk)
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r_spd_2 <= r_spd;
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`else
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wire rd_input_2, rd_valid_2, r_spd_2;
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assign rd_input_2 = rd_input;
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assign rd_valid_2 = rd_valid;
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assign r_spd_2 = rd_spd;
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((state == `EQSPI_IDLE)||(rd_valid))
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if ((state == `EQSPI_IDLE)||(rd_valid_2))
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r_input <= 31'h00;
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r_input <= 31'h00;
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else if ((rd_input)&&(r_spd))
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else if ((rd_input_2)&&(r_spd_2))
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r_input <= { r_input[26:0], i_dat };
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r_input <= { r_input[26:0], i_dat };
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else if (rd_input)
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else if (rd_input_2)
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r_input <= { r_input[29:0], i_miso };
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r_input <= { r_input[29:0], i_miso };
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if ((rd_valid)&&(r_spd))
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if ((rd_valid)&&(rd_spd))
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o_word <= { r_input[27:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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else if (rd_valid)
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else if (rd_valid)
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o_word <= { r_input[30:0], i_miso };
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o_word <= { r_input[30:0], i_miso };
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end
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end
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assign o_valid = rd_valid;
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assign o_valid = rd_valid_2;
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endmodule
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endmodule
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