| Line 68... |
Line 68... |
input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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input i_spd; // 0 -> normal QPI, 1 -> QSPI
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input i_spd; // 0 -> normal QPI, 1 -> QSPI
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input i_dir; // 0 -> read, 1 -> write to SPI
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input i_dir; // 0 -> read, 1 -> write to SPI
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input i_recycle; // 0 = 20ns, 1 = 50ns
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input i_recycle; // 0 = 20ns, 1 = 50ns
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output reg [31:0] o_word;
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output reg [31:0] o_word;
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output wire o_valid;
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output reg o_valid;
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output reg o_busy;
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output reg o_busy;
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// Interface with the QSPI lines
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// Interface with the QSPI lines
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output reg o_sck;
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output reg o_sck;
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output reg o_cs_n;
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output reg o_cs_n;
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output reg [1:0] o_mod;
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output reg [1:0] o_mod;
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| Line 296... |
Line 296... |
end
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end
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*/
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*/
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end
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end
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`define EXTRA_DELAY
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`define EXTRA_DELAY
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wire rd_input_N, rd_valid_N, r_spd_N;
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`ifdef EXTRA_DELAY
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`ifdef EXTRA_DELAY
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reg rd_input_2, rd_valid_2, r_spd_2;
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reg [2:0] rd_input_p, rd_valid_p, r_spd_p;
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always @(posedge i_clk)
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always @(posedge i_clk)
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rd_input_2 <= rd_input;
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rd_input_p <= { rd_input_p[1:0], rd_input };
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always @(posedge i_clk)
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always @(posedge i_clk)
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rd_valid_2 <= rd_valid;
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rd_valid_p <= { rd_valid_p[1:0], rd_valid };
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_spd_2 <= r_spd;
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r_spd_p <= { r_spd_p[1:0], r_spd };
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|
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assign rd_input_N = rd_input_p[2];
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assign rd_valid_N = rd_valid_p[2];
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assign r_spd_N = r_spd_p[2];
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`else
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`else
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wire rd_input_2, rd_valid_2, r_spd_2;
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assign rd_input_N = rd_input;
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assign rd_input_2 = rd_input;
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assign rd_valid_N = rd_valid;
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assign rd_valid_2 = rd_valid;
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assign r_spd_N = rd_spd;
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assign r_spd_2 = rd_spd;
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`endif
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`endif
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|
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
|
begin
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if ((state == `EQSPI_IDLE)||(rd_valid_2))
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// if ((state == `EQSPI_IDLE)||(rd_valid_N))
|
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if (o_valid)
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r_input <= 31'h00;
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r_input <= 31'h00;
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else if ((rd_input_2)&&(r_spd_2))
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if ((rd_input_N)&&(r_spd_N))
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r_input <= { r_input[26:0], i_dat };
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r_input <= { r_input[26:0], i_dat };
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else if (rd_input_2)
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else if (rd_input_N)
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r_input <= { r_input[29:0], i_miso };
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r_input <= { r_input[29:0], i_miso };
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|
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if ((rd_valid)&&(rd_spd))
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if ((rd_valid_N)&&(r_spd_N))
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o_word <= { r_input[27:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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else if (rd_valid)
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else if (rd_valid_N)
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o_word <= { r_input[30:0], i_miso };
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o_word <= { r_input[30:0], i_miso };
|
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o_valid <= rd_valid_N;
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end
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end
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|
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assign o_valid = rd_valid_2;
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|
|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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