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Line 37... |
///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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module memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data);
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o_wb_ack, o_wb_stall, o_wb_data);
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parameter AW=15, DW=32;
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parameter AW=15, DW=32, EXTRACLOCK= 0;
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input i_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input i_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input [(AW-1):0] i_wb_addr;
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input [(AW-1):0] i_wb_addr;
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input [(DW-1):0] i_wb_data;
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input [(DW-1):0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [(DW-1):0] o_wb_data;
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output reg [(DW-1):0] o_wb_data;
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wire w_wstb, w_stb;
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wire [(DW-1):0] w_data;
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wire [(AW-1):0] w_addr;
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generate
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if (EXTRACLOCK == 0)
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begin
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assign w_wstb = (i_wb_stb)&&(i_wb_we);
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assign w_stb = i_wb_stb;
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assign w_addr = i_wb_addr;
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assign w_data = i_wb_data;
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end else begin
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reg last_wstb, last_stb;
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reg last_wstb, last_stb;
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always @(posedge i_clk)
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always @(posedge i_clk)
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last_wstb <= (i_wb_stb)&&(i_wb_we);
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last_wstb <= (i_wb_stb)&&(i_wb_we);
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always @(posedge i_clk)
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always @(posedge i_clk)
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last_stb <= (i_wb_stb);
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last_stb <= (i_wb_stb);
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always @(posedge i_clk)
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always @(posedge i_clk)
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last_data <= i_wb_data;
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last_data <= i_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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last_addr <= i_wb_addr;
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last_addr <= i_wb_addr;
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assign w_wstb = last_wstb;
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assign w_stb = last_stb;
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assign w_addr = last_addr;
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assign w_data = last_data;
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end endgenerate
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reg [(DW-1):0] mem [0:((1<<AW)-1)];
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reg [(DW-1):0] mem [0:((1<<AW)-1)];
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_data <= mem[last_addr];
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o_wb_data <= mem[w_addr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (last_wstb)
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if (w_wstb)
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mem[last_addr] <= last_data;
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mem[w_addr] <= w_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (last_stb);
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o_wb_ack <= (w_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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endmodule
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endmodule
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