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https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [rxehwmac.v] - Diff between revs 31 and 33
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| Rev 31 |
Rev 33 |
| Line 47... |
Line 47... |
output reg o_v;
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output reg o_v;
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output reg [3:0] o_d;
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output reg [3:0] o_d;
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output wire o_err;
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output wire o_err;
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output reg o_broadcast;
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output reg o_broadcast;
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wire [47:0] mac_remapped;
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assign mac_remapped[47:44] = i_hwmac[43:40];
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assign mac_remapped[43:40] = i_hwmac[47:44];
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assign mac_remapped[39:36] = i_hwmac[35:32];
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assign mac_remapped[35:32] = i_hwmac[39:36];
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assign mac_remapped[31:28] = i_hwmac[27:24];
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assign mac_remapped[27:24] = i_hwmac[31:28];
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assign mac_remapped[23:20] = i_hwmac[19:16];
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assign mac_remapped[19:16] = i_hwmac[23:20];
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assign mac_remapped[15:12] = i_hwmac[11: 8];
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assign mac_remapped[11: 8] = i_hwmac[15:12];
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assign mac_remapped[ 7: 4] = i_hwmac[ 3: 0];
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assign mac_remapped[ 3: 0] = i_hwmac[ 7: 4];
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reg [47:0] r_hwmac;
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reg [47:0] r_hwmac;
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reg r_cancel, r_err, r_hwmatch, r_broadcast;
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reg r_cancel, r_err, r_hwmatch, r_broadcast;
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reg [19:0] r_buf;
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reg [19:0] r_buf;
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reg [29:0] r_p;
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reg [29:0] r_p;
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| Line 68... |
Line 83... |
r_hwmatch <= 1'b0;
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r_hwmatch <= 1'b0;
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if (4'hf != i_d)
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if (4'hf != i_d)
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r_broadcast<= 1'b0;
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r_broadcast<= 1'b0;
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end
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end
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if ((i_v)&&(r_p[11]))
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r_hwmac <= { r_hwmac[43:0], 4'h0 };
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r_err <= (i_en)&&(!r_hwmatch)&&(!r_broadcast)&&(i_v);
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r_err <= (i_en)&&(!r_hwmatch)&&(!r_broadcast)&&(i_v);
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o_broadcast <= (r_broadcast)&&(!r_p[11])&&(i_v);
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o_broadcast <= (r_broadcast)&&(!r_p[11])&&(i_v);
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r_buf <= { r_buf[14:0], i_v, i_d };
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r_buf <= { r_buf[14:0], i_v, i_d };
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if (((!i_v)&&(!o_v))||(i_cancel))
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if (((!i_v)&&(!o_v))||(i_cancel))
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begin
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begin
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r_p <= 30'h3fff_ffff;
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r_p <= 30'h3fff_ffff;
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r_hwmac <= i_hwmac;
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r_hwmac <= mac_remapped;
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r_hwmatch <= 1'b1;
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r_hwmatch <= 1'b1;
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r_broadcast <= 1'b1;
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r_broadcast <= 1'b1;
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r_buf[ 4] <= 1'b0;
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r_buf[ 4] <= 1'b0;
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r_buf[ 9] <= 1'b0;
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r_buf[ 9] <= 1'b0;
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r_buf[14] <= 1'b0;
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r_buf[14] <= 1'b0;
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