////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wboled.v
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// Filename: wboled.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: To provide a *very* simplified controller for a PMod OLEDrgb.
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// Purpose: To provide a *very* simplified controller for a PMod OLEDrgb.
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// This controller implements four registers (described below),
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// This controller implements four registers (described below),
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// although it might feel like only two in practice. As with all of our
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// although it might feel like only two in practice. As with all of our
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// other wishbone work, all transactions are 32-bits--even though, as an
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// other wishbone work, all transactions are 32-bits--even though, as an
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// example, the data word for the device is only ever 16-bits long.
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// example, the data word for the device is only ever 16-bits long.
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//
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//
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// The device control, outlined below, is also colored by two facts:
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// The device control, outlined below, is also colored by two facts:
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// 1. There is no means to read from the device. Sure, the chip on the
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// 1. There is no means to read from the device. Sure, the chip on the
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// PMod has a full read/write bus, but it hasn't been entirely
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// PMod has a full read/write bus, but it hasn't been entirely
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// wired to the PMod pins. This was probably done so that the
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// wired to the PMod pins. This was probably done so that the
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// interface could handle the paucity of pins available, but for
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// interface could handle the paucity of pins available, but for
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// whatever reason, there's no way to read from the device.
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// whatever reason, there's no way to read from the device.
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// 2. The device is controlled by a SPI port, but with an extra wire that
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// 2. The device is controlled by a SPI port, but with an extra wire that
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// determines whether or not you are writing to the control or the
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// determines whether or not you are writing to the control or the
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// data port on the device. Hence the four wire SPI protocol has
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// data port on the device. Hence the four wire SPI protocol has
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// lost the MISO wire and gained a Data / Control (N) (or dcn)
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// lost the MISO wire and gained a Data / Control (N) (or dcn)
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// wire.
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// wire.
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// 3. As implemented, the device also has two power control wires and a
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// 3. As implemented, the device also has two power control wires and a
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// reset wire. The reset wire is negative logic. Without setting
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// reset wire. The reset wire is negative logic. Without setting
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// the PMOD-Enable wire high, the board has no power. The
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// the PMOD-Enable wire high, the board has no power. The
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// VCCEN pin is not to be set high without PMOD-Enable high.
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// VCCEN pin is not to be set high without PMOD-Enable high.
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// Finally, setting reset low (with PMod-Enable high), places the
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// Finally, setting reset low (with PMod-Enable high), places the
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// device into a reset condition.
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// device into a reset condition.
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//
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//
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// The design of the controller, as with the design of other controllers
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// The design of the controller, as with the design of other controllers
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// we have built, is focused around the design principles:
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// we have built, is focused around the design principles:
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// 1. Use the bottom 23 bits of a word for the command, if possible.
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// 1. Use the bottom 23 bits of a word for the command, if possible.
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// Such commands can be loaded into registers with simple LDI
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// Such commands can be loaded into registers with simple LDI
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// instructions. Even better, restrict any status results from the
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// instructions. Even better, restrict any status results from the
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// device to 18 bits, so that instructions that use immediates
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// device to 18 bits, so that instructions that use immediates
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// such as TEST #,Rx, can use these immediates.
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// such as TEST #,Rx, can use these immediates.
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// 2. Protect against inadvertant changes to the power port. For this,
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// 2. Protect against inadvertant changes to the power port. For this,
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// we insist that a minimum of two bits be high to change the
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// we insist that a minimum of two bits be high to change the
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// power port bits, and that just reading from the port and
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// power port bits, and that just reading from the port and
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// writing back with a changed power bit is not sufficient to
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// writing back with a changed power bit is not sufficient to
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// change the power.
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// change the power.
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// 3. Permit atomic changes to the individual power control bits,
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// 3. Permit atomic changes to the individual power control bits,
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// by outlining which exact bits change upon any write, and
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// by outlining which exact bits change upon any write, and
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// permitting only the bits specified to change.
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// permitting only the bits specified to change.
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// 4. Don't stall the bus. So, if a command comes in and the
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// 4. Don't stall the bus. So, if a command comes in and the
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// device is busy, we'll ignore the command. It is up to the
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// device is busy, we'll ignore the command. It is up to the
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// user to make certain the device isn't fed faster than it is
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// user to make certain the device isn't fed faster than it is
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// able. (Perhaps the user wishes to add a FIFO?)
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// able. (Perhaps the user wishes to add a FIFO?)
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// 5. Finally, build this so that either a FIFO or DMA could control it.
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// 5. Finally, build this so that either a FIFO or DMA could control it.
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//
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//
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// Registers:
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// Registers:
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// 0. Control -- There are several types of control commands to/from
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// 0. Control -- There are several types of control commands to/from
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// the device, all separated and determined by how many bytes are
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// the device, all separated and determined by how many bytes are
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// to be sent to the device for the said command. Commands written
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// to be sent to the device for the said command. Commands written
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// to the control port of the device are initiated by writes
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// to the control port of the device are initiated by writes
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// to this register.
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// to this register.
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//
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//
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// - Writes of all { 24'h00, data[7:0] } send the single byte
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// - Writes of all { 24'h00, data[7:0] } send the single byte
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// data[7:0] to the device.
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// data[7:0] to the device.
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// - Writes of { 16'h01, data[15:0] } send two bytes,
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// - Writes of { 16'h01, data[15:0] } send two bytes,
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// data[15:0], to the device.
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// data[15:0], to the device.
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// - Writes of { 4'h2, 4'hx, data[23:0] } send three bytes,
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// - Writes of { 4'h2, 4'hx, data[23:0] } send three bytes,
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// data[23:0], to the device.
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// data[23:0], to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send four bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send four bytes,
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// data[23:0], then r_a[31:24] to the device.
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// data[23:0], then r_a[31:24] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send five bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send five bytes,
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// data[23:0], then r_a[31:16] to the device.
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// data[23:0], then r_a[31:16] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send six bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send six bytes,
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// data[23:0], then r_a[31:8] to the device.
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// data[23:0], then r_a[31:8] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send seven bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send seven bytes,
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// data[23:0], then r_a[31:0] to the device.
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// data[23:0], then r_a[31:0] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send eight bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send eight bytes,
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// data[23:0], r_a[31:16], then r_b[31:24] to the device.
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// data[23:0], r_a[31:16], then r_b[31:24] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send nine bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send nine bytes,
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// data[23:0], r_a[31:16], then r_b[31:16] to the device.
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// data[23:0], r_a[31:16], then r_b[31:16] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send ten bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send ten bytes,
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// data[23:0], r_a[31:16], then r_b[31:8] to the device.
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// data[23:0], r_a[31:16], then r_b[31:8] to the device.
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// - Writes of { 4'h3, 4'hx, data[23:0] } send eleven bytes,
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// - Writes of { 4'h3, 4'hx, data[23:0] } send eleven bytes,
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// data[23:0], r_a[31:16], then r_b[31:0] to the device.
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// data[23:0], r_a[31:16], then r_b[31:0] to the device.
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//
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//
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// 1. A This register is used, just like the B register below, for
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// 1. A This register is used, just like the B register below, for
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// setting up commands that send multiple bytes to the device.
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// setting up commands that send multiple bytes to the device.
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// Be aware that the high order bits/bytes will be sent first.
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// Be aware that the high order bits/bytes will be sent first.
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// This is one of the few registers that may be read with meaning.
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// This is one of the few registers that may be read with meaning.
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// Once the word is written, however, the register is cleared.
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// Once the word is written, however, the register is cleared.
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//
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//
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// 2. B This is the same as the A register, save on writes the A
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// 2. B This is the same as the A register, save on writes the A
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// register will be written first before any bits from the B
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// register will be written first before any bits from the B
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// register. As with the A register, this value is cleared upon
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// register. As with the A register, this value is cleared upon
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// any write--regardless of whether its value is used in the
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// any write--regardless of whether its value is used in the
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// write.
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// write.
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//
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//
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// 3. Data --- This is both the data and the power control register.
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// 3. Data --- This is both the data and the power control register.
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//
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//
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// To write data to the graphics data RAM within the device,
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// To write data to the graphics data RAM within the device,
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// simply write a 16'bit word: { 16'h00, data[15:0] } to this
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// simply write a 16'bit word: { 16'h00, data[15:0] } to this
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// port.
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// port.
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//
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//
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// To change the three power bits, {reset, vccen, pmoden},
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// To change the three power bits, {reset, vccen, pmoden},
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// you must also set a 1'b1 in the corresponding bit position from
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// you must also set a 1'b1 in the corresponding bit position from
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// bit 16-18. Hence a:
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// bit 16-18. Hence a:
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//
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//
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// 32'h010001 sets the pmod enable bit, whereas 32'h010000 clears
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// 32'h010001 sets the pmod enable bit, whereas 32'h010000 clears
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// it.
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// it.
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// 32'h020002 sets the vcc bit, whereas 32'h010000 clears it.
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// 32'h020002 sets the vcc bit, whereas 32'h010000 clears it.
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//
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//
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// Multiple of the power bits can be changed at once. Each
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// Multiple of the power bits can be changed at once. Each
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// respective bit is only changed if it's change enable bit is
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// respective bit is only changed if it's change enable bit is
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// also high.
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// also high.
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wboled(i_clk, i_cyc, i_stb, i_we, i_addr, i_data,
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module wboled(i_clk, i_cyc, i_stb, i_we, i_addr, i_data,
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o_ack, o_stall, o_data,
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o_ack, o_stall, o_data,
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o_sck, o_cs_n, o_mosi, o_dbit,
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o_sck, o_cs_n, o_mosi, o_dbit,
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o_pwr, o_int);
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o_pwr, o_int);
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parameter CBITS=8, // 2^4*2@6.25ns -> 200ns/clock > 150ns min
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parameter CBITS=4, // 2^4*13ns -> 208ns/clock > 150ns min
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EXTRA_BUS_CLOCK = 0;
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EXTRA_BUS_CLOCK = 0;
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input i_clk, i_cyc, i_stb, i_we;
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input i_clk, i_cyc, i_stb, i_we;
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input [1:0] i_addr;
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input [1:0] i_addr;
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input [31:0] i_data;
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input [31:0] i_data;
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output reg o_ack;
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output reg o_ack;
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output wire o_stall;
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output wire o_stall;
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output reg [31:0] o_data;
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output reg [31:0] o_data;
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output wire o_sck, o_cs_n, o_mosi, o_dbit;
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output wire o_sck, o_cs_n, o_mosi, o_dbit;
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output reg [2:0] o_pwr;
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output reg [2:0] o_pwr;
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output wire o_int;
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output wire o_int;
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reg dev_wr, dev_dbit;
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reg dev_wr, dev_dbit;
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reg [31:0] dev_word;
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reg [31:0] dev_word;
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reg [1:0] dev_len;
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reg [1:0] dev_len;
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wire dev_busy;
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wire dev_busy;
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lloled #(CBITS)
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lloled #(CBITS)
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lwlvl(i_clk, dev_wr, dev_dbit, dev_word, dev_len, dev_busy,
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lwlvl(i_clk, dev_wr, dev_dbit, dev_word, dev_len, dev_busy,
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o_sck, o_cs_n, o_mosi, o_dbit);
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o_sck, o_cs_n, o_mosi, o_dbit);
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|
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wire wb_stb, wb_we;
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wire wb_stb, wb_we;
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wire [31:0] wb_data;
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wire [31:0] wb_data;
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wire [1:0] wb_addr;
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wire [1:0] wb_addr;
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// I've thought about bumping this from a clock at <= 100MHz up to a
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// I've thought about bumping this from a clock at <= 100MHz up to a
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// clock near 200MHz. Doing so requires an extra clock to come off
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// clock near 200MHz. Doing so requires an extra clock to come off
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// the bus--the bus fanout is just too wide otherwise. However,
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// the bus--the bus fanout is just too wide otherwise. However,
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// if you don't need to ... why take the extra clock cycle? Hence
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// if you don't need to ... why take the extra clock cycle? Hence
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// this little snippet of code allows the rest of the controller
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// this little snippet of code allows the rest of the controller
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// to work at 200MHz or 100MHz as need be.
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// to work at 200MHz or 100MHz as need be.
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generate
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generate
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if (EXTRA_BUS_CLOCK != 0)
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if (EXTRA_BUS_CLOCK != 0)
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begin
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begin
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reg r_wb_stb, r_wb_we;
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reg r_wb_stb, r_wb_we;
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reg [31:0] r_wb_data;
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reg [31:0] r_wb_data;
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reg [1:0] r_wb_addr;
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reg [1:0] r_wb_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_wb_stb <= i_stb;
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r_wb_stb <= i_stb;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_wb_we <= i_we;
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r_wb_we <= i_we;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_wb_data <= i_data;
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r_wb_data <= i_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_wb_addr <= i_addr;
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r_wb_addr <= i_addr;
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|
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assign wb_stb = r_wb_stb;
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assign wb_stb = r_wb_stb;
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assign wb_we = r_wb_we;
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assign wb_we = r_wb_we;
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assign wb_data = r_wb_data;
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assign wb_data = r_wb_data;
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assign wb_addr = r_wb_addr;
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assign wb_addr = r_wb_addr;
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end else begin
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end else begin
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assign wb_stb = i_stb;
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assign wb_stb = i_stb;
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assign wb_we = i_we;
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assign wb_we = i_we;
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assign wb_data = i_data;
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assign wb_data = i_data;
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assign wb_addr = i_addr;
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assign wb_addr = i_addr;
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end endgenerate
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end endgenerate
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reg r_busy;
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reg r_busy;
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reg [3:0] r_len;
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reg [3:0] r_len;
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|
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//
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//
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// Handle registers A & B. These are set either upon a write, or
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// Handle registers A & B. These are set either upon a write, or
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// cleared (set to zero) upon any command to the control register.
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// cleared (set to zero) upon any command to the control register.
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//
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//
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reg [31:0] r_a, r_b;
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reg [31:0] r_a, r_b;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_stb)&&(wb_we))
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if ((wb_stb)&&(wb_we))
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begin
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begin
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if (wb_addr[1:0]==2'b01)
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if (wb_addr[1:0]==2'b01)
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r_a <= wb_data;
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r_a <= wb_data;
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if (wb_addr[1:0]==2'b10)
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if (wb_addr[1:0]==2'b10)
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r_b <= wb_data;
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r_b <= wb_data;
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end else if (r_cstb)
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end else if (r_cstb)
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begin
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begin
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r_a <= 32'h00;
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r_a <= 32'h00;
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r_b <= 32'h00;
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r_b <= 32'h00;
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end
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end
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|
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//
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//
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// Handle reads from our device. These really aren't all that
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// Handle reads from our device. These really aren't all that
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// interesting, but ... we can do them anyway. We attempt to provide
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// interesting, but ... we can do them anyway. We attempt to provide
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// some sort of useful value here. For example, upon reading r_a or
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// some sort of useful value here. For example, upon reading r_a or
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// r_b, you can read the current value(s) of those register(s).
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// r_b, you can read the current value(s) of those register(s).
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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case (wb_addr)
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case (wb_addr)
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2'b00: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 1'b0, o_dbit, !o_cs_n, r_busy };
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2'b00: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 1'b0, o_dbit, !o_cs_n, r_busy };
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2'b01: o_data <= r_a;
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2'b01: o_data <= r_a;
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2'b10: o_data <= r_b;
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2'b10: o_data <= r_b;
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2'b11: o_data <= { 16'h00, 13'h0, o_pwr };
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2'b11: o_data <= { 16'h00, 13'h0, o_pwr };
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endcase
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endcase
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end
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end
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|
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initial o_ack = 1'b0;
|
initial o_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_ack <= wb_stb;
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o_ack <= wb_stb;
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assign o_stall = 1'b0;
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assign o_stall = 1'b0;
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|
|
reg r_cstb, r_dstb, r_pstb, r_pre_busy;
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reg r_cstb, r_dstb, r_pstb, r_pre_busy;
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reg [18:0] r_data;
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reg [18:0] r_data;
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initial r_cstb = 1'b0;
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initial r_cstb = 1'b0;
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initial r_dstb = 1'b0;
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initial r_dstb = 1'b0;
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initial r_pstb = 1'b0;
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initial r_pstb = 1'b0;
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initial r_pre_busy = 1'b0; // Used to clear the interrupt a touch earlier
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initial r_pre_busy = 1'b0; // Used to clear the interrupt a touch earlier
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// The control strobe. This will be true if we need to command a
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// The control strobe. This will be true if we need to command a
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// control interaction.
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// control interaction.
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_cstb <= (wb_stb)&&(wb_we)&&(wb_addr[1:0]==2'b00);
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r_cstb <= (wb_stb)&&(wb_we)&&(wb_addr[1:0]==2'b00);
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// The data strobe, true if we need to command a data interaction.
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// The data strobe, true if we need to command a data interaction.
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_dstb <= (wb_stb)&&(wb_we)&&(wb_addr[1:0]==2'b11)&&(wb_data[18:16]==3'h0);
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r_dstb <= (wb_stb)&&(wb_we)&&(wb_addr[1:0]==2'b11)&&(wb_data[18:16]==3'h0);
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// The power strobe. True if we are about to adjust the power and/or
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// The power strobe. True if we are about to adjust the power and/or
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// reset bits.
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// reset bits.
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always @(posedge i_clk) // Power strobe, change power settings
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always @(posedge i_clk) // Power strobe, change power settings
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r_pstb <= (wb_stb)&&(wb_we)&&(wb_addr[1:0]==2'b11)&&(wb_data[18:16]!=3'h0);
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r_pstb <= (wb_stb)&&(wb_we)&&(wb_addr[1:0]==2'b11)&&(wb_data[18:16]!=3'h0);
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// Pre-busy: true if either r_cstb or r_dstb is true, and true on the
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// Pre-busy: true if either r_cstb or r_dstb is true, and true on the
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// same clock they are true. This is to support our interrupt, by
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// same clock they are true. This is to support our interrupt, by
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// clearing the interrupt one clock earlier--lest the DMA decide to send
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// clearing the interrupt one clock earlier--lest the DMA decide to send
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// two words our way instead of one.
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// two words our way instead of one.
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_pre_busy <= (wb_stb)&&(wb_we)&&
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r_pre_busy <= (wb_stb)&&(wb_we)&&
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((wb_addr[1:0]==2'b11)||(wb_addr[1:0]==2'b00));
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((wb_addr[1:0]==2'b11)||(wb_addr[1:0]==2'b00));
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// But ... to use these strobe values, we are now one more clock
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// But ... to use these strobe values, we are now one more clock
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// removed from the bus. We need something that matches this, so let's
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// removed from the bus. We need something that matches this, so let's
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// delay our bus data one more clock 'til the time when we actually use
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// delay our bus data one more clock 'til the time when we actually use
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// it.
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// it.
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_data <= wb_data[18:0];
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r_data <= wb_data[18:0];
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initial o_pwr = 3'h0;
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initial o_pwr = 3'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (r_pstb)
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if (r_pstb)
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o_pwr <= ((o_pwr)&(~r_data[18:16]))
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o_pwr <= ((o_pwr)&(~r_data[18:16]))
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|((r_data[2:0])&(r_data[18:16]));
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|((r_data[2:0])&(r_data[18:16]));
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// Sadly, because our commands can have a whole slew of different
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// Sadly, because our commands can have a whole slew of different
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// lengths, and because these lengths can be ... difficult to
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// lengths, and because these lengths can be ... difficult to
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// decipher from the command (especially the first two lengths),
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// decipher from the command (especially the first two lengths),
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// this quick case statement is needed to decode the amount of bytes
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// this quick case statement is needed to decode the amount of bytes
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// that will be sent.
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// that will be sent.
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reg [3:0] b_len;
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reg [3:0] b_len;
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always @(posedge i_clk)
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always @(posedge i_clk)
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casez(wb_data[31:28])
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casez(wb_data[31:28])
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4'b0000: b_len <= (wb_data[16])? 4'h2:4'h1;
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4'b0000: b_len <= (wb_data[16])? 4'h2:4'h1;
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4'b0001: b_len <= 4'h2;
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4'b0001: b_len <= 4'h2;
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4'b0010: b_len <= 4'h3;
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4'b0010: b_len <= 4'h3;
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4'b0011: b_len <= 4'h4;
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4'b0011: b_len <= 4'h4;
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4'b0100: b_len <= 4'h5;
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4'b0100: b_len <= 4'h5;
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4'b0101: b_len <= 4'h6;
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4'b0101: b_len <= 4'h6;
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4'b0110: b_len <= 4'h7;
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4'b0110: b_len <= 4'h7;
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4'b0111: b_len <= 4'h8;
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4'b0111: b_len <= 4'h8;
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4'b1000: b_len <= 4'h9;
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4'b1000: b_len <= 4'h9;
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4'b1001: b_len <= 4'ha;
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4'b1001: b_len <= 4'ha;
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4'b1010: b_len <= 4'hb;
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4'b1010: b_len <= 4'hb;
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default: b_len <= 4'h0;
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default: b_len <= 4'h0;
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endcase
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endcase
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//
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//
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// On the next clock, we're going to set our data register to
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// On the next clock, we're going to set our data register to
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// whatever's in register A, and B, and ... something of the data
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// whatever's in register A, and B, and ... something of the data
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// written to the control register. Because this must all be
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// written to the control register. Because this must all be
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// written on the most-significant bits of a word, we pause a moment
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// written on the most-significant bits of a word, we pause a moment
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// here to move the control word that was writen to our bus up
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// here to move the control word that was writen to our bus up
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// by an amount given by the length of our message. That way, you
|
// by an amount given by the length of our message. That way, you
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// can write to the bottom bits of the register, and yet still end
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// can write to the bottom bits of the register, and yet still end
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// up in the top several bits of the following register.
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// up in the top several bits of the following register.
|
//
|
//
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reg [23:0] c_data;
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reg [23:0] c_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_data[31:29] != 3'h0)
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if (wb_data[31:29] != 3'h0)
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c_data <= wb_data[23:0];
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c_data <= wb_data[23:0];
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else if (wb_data[16])
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else if (wb_data[16])
|
c_data <= { wb_data[15:0], 8'h00 };
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c_data <= { wb_data[15:0], 8'h00 };
|
else
|
else
|
c_data <= { wb_data[7:0], 16'h00 };
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c_data <= { wb_data[7:0], 16'h00 };
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|
|
//
|
//
|
// Finally, after massaging the incoming data off our bus, we finally
|
// Finally, after massaging the incoming data off our bus, we finally
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// get to controlling the lower level controller and sending the
|
// get to controlling the lower level controller and sending the
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// data to the device itself.
|
// data to the device itself.
|
//
|
//
|
// The basic idea is this: we use r_busy to know if we are in the
|
// The basic idea is this: we use r_busy to know if we are in the
|
// middle of an operation, or whether or not we will be responsive to
|
// middle of an operation, or whether or not we will be responsive to
|
// the bus. r_sreg holds the data we wish to send, and r_len the
|
// the bus. r_sreg holds the data we wish to send, and r_len the
|
// number of bytes within r_sreg that remain to be sent. The controller
|
// number of bytes within r_sreg that remain to be sent. The controller
|
// will accept up to 32-bits at a time, so once we issue a command
|
// will accept up to 32-bits at a time, so once we issue a command
|
// (dev_wr & !dev_busy), we transition to either the next command.
|
// (dev_wr & !dev_busy), we transition to either the next command.
|
// Once all the data has been sent, and the device is now idle, we
|
// Once all the data has been sent, and the device is now idle, we
|
// clear r_busy and therefore become responsive to the bus again.
|
// clear r_busy and therefore become responsive to the bus again.
|
//
|
//
|
//
|
//
|
reg [87:0] r_sreg; // Composed of 24-bits, 32-bits, and 32-bits
|
reg [87:0] r_sreg; // Composed of 24-bits, 32-bits, and 32-bits
|
initial r_busy = 1'b0;
|
initial r_busy = 1'b0;
|
initial dev_wr = 1'b1;
|
initial dev_wr = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
dev_wr <= 1'b0;
|
dev_wr <= 1'b0;
|
if ((~r_busy)&&(r_cstb))
|
if ((~r_busy)&&(r_cstb))
|
begin
|
begin
|
dev_dbit <= 1'b0;
|
dev_dbit <= 1'b0;
|
r_sreg <= { c_data[23:0], r_a, r_b };
|
r_sreg <= { c_data[23:0], r_a, r_b };
|
r_len <= b_len;
|
r_len <= b_len;
|
r_busy <= (b_len != 4'h0);
|
r_busy <= (b_len != 4'h0);
|
end else if ((~r_busy)&&(r_dstb))
|
end else if ((~r_busy)&&(r_dstb))
|
begin
|
begin
|
dev_dbit <= 1'b1;
|
dev_dbit <= 1'b1;
|
r_sreg <= { r_data[15:0], 72'h00 };
|
r_sreg <= { r_data[15:0], 72'h00 };
|
r_len <= 4'h2;
|
r_len <= 4'h2;
|
r_busy <= 1'b1;
|
r_busy <= 1'b1;
|
end else if ((r_busy)&&(!dev_busy))
|
end else if ((r_busy)&&(!dev_busy))
|
begin
|
begin
|
// Issue the command to write up to 32-bits at a time
|
// Issue the command to write up to 32-bits at a time
|
dev_wr <= (r_len != 4'h0);
|
dev_wr <= (r_len != 4'h0);
|
dev_word <= r_sreg[87:56];
|
dev_word <= r_sreg[87:56];
|
r_sreg <= { r_sreg[55:0], 32'h00 };
|
r_sreg <= { r_sreg[55:0], 32'h00 };
|
dev_len <= (r_len > 4'h4)? 2'b11:(r_len[1:0]+2'b11);
|
dev_len <= (r_len > 4'h4)? 2'b11:(r_len[1:0]+2'b11);
|
if (dev_wr)
|
if (dev_wr)
|
r_len <= (r_len > 4'h4) ? (r_len-4'h4):0;
|
r_len <= (r_len > 4'h4) ? (r_len-4'h4):0;
|
r_busy <= (dev_wr)||(r_len != 4'h0)&&(!dev_wr);
|
r_busy <= (dev_wr)||(r_len != 4'h0)&&(!dev_wr);
|
end else if (r_busy) // & dev_busy
|
end else if (r_busy) // & dev_busy
|
begin
|
begin
|
dev_wr <= (r_len != 4'h0);
|
dev_wr <= (r_len != 4'h0);
|
dev_len <= (r_len > 4'h4)? 2'b11:(r_len[1:0]+2'b11);
|
dev_len <= (r_len > 4'h4)? 2'b11:(r_len[1:0]+2'b11);
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Here, we pick a self-clearing interrupt input. This will set the
|
// Here, we pick a self-clearing interrupt input. This will set the
|
// interrupt any time we are idle, and will automatically clear itself
|
// interrupt any time we are idle, and will automatically clear itself
|
// any time we become busy. This should be sufficient to allow the
|
// any time we become busy. This should be sufficient to allow the
|
// DMA controller to send things to the card.
|
// DMA controller to send things to the card.
|
//
|
//
|
// Of course ... if you are not running in any sort of interrupt mode,
|
// Of course ... if you are not running in any sort of interrupt mode,
|
// you *could* just ignore this line and poll the busy bit instead.
|
// you *could* just ignore this line and poll the busy bit instead.
|
//
|
//
|
assign o_int = (~r_busy)&&(!r_pre_busy);
|
assign o_int = (~r_busy)&&(!r_pre_busy);
|
|
|
endmodule
|
endmodule
|
|
|
