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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbscope.v
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// Filename: wbscope.v
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//
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//
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// Project: FPGA Library of Routines
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// Project: WBScope, a wishbone hosted scope
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//
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//
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// Purpose: This is a generic/library routine for providing a bus accessed
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// Purpose: This is a generic/library routine for providing a bus accessed
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// 'scope' or (perhaps more appropriately) a bus accessed logic
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// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer.
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// analyzer. The general operation is such that this 'scope' can
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// The general operation is such that this 'scope' can record and report
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// record and report on any 32 bit value transiting through the
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// on any 32 bit value transiting through the FPGA. Once started and
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// FPGA. Once started and reset, the scope records a copy of the
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// reset, the scope records a copy of the input data every time the clock
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// input data every time the clock ticks with the circuit enabled.
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// ticks with the circuit enabled. That is, it records these values up
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// That is, it records these values up until the trigger. Once
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// until the trigger. Once the trigger goes high, the scope will record
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// the trigger goes high, the scope will record for bw_holdoff
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// for bw_holdoff more counts before stopping. Values may then be read
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// more counts before stopping. Values may then be read from the
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// from the buffer, oldest to most recent. After reading, the scope may
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// buffer, oldest to most recent. After reading, the scope may
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// then be reset for another run.
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// then be reset for another run.
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//
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//
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// In general, therefore, operation happens in this fashion:
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// In general, therefore, operation happens in this fashion:
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// 1. A reset is issued.
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// 1. A reset is issued.
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// 2. Recording starts, in a circular buffer, and continues until
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// 2. Recording starts, in a circular buffer, and continues until
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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bw_disable_trigger, bw_reset_complete;
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bw_disable_trigger, bw_reset_complete;
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reg [22:0] br_config;
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reg [22:0] br_config;
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wire [19:0] bw_holdoff;
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wire [19:0] bw_holdoff;
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initial br_config = DEFAULT_HOLDOFF;
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initial br_config = DEFAULT_HOLDOFF;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
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if ((i_wb_stb)&&(~i_wb_addr))
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begin
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begin
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if (i_wb_we)
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if (i_wb_we)
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br_config <= { i_wb_data[31],
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br_config <= { i_wb_data[31],
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(i_wb_data[27]),
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(i_wb_data[27]),
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i_wb_data[26],
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i_wb_data[26],
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(* ASYNC_REG="TRUE" *) reg [19:0] counter;// This is unsigned
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(* ASYNC_REG="TRUE" *) reg [19:0] counter;// This is unsigned
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initial dr_stopped = 1'b0;
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initial dr_stopped = 1'b0;
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initial counter = 20'h0000;
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initial counter = 20'h0000;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dw_reset)
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if (dw_reset)
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begin
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counter <= 0;
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counter <= 0;
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dr_stopped <= 1'b0;
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else if ((i_ce)&&(dr_triggered)&&(~dr_stopped))
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end else if ((i_ce)&&(dr_triggered))
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begin // MUST BE a < and not <=, so that we can keep this w/in
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begin // MUST BE a < and not <=, so that we can keep this w/in
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// 20 bits. Else we'd need to add a bit to comparison
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// 20 bits. Else we'd need to add a bit to comparison
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// here.
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// here.
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if (counter < bw_holdoff)
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counter <= counter + 20'h01;
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counter <= counter + 20'h01;
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else
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dr_stopped <= 1'b1;
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end
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end
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always @(posedge i_clk)
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if ((~dr_triggered)||(dw_reset))
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dr_stopped <= 1'b0;
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else if (i_ce)
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dr_stopped <= (counter+20'd1 >= bw_holdoff);
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else
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dr_stopped <= (counter >= bw_holdoff);
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//
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//
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// Actually do our writes to memory. Record, via 'primed' when
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// Actually do our writes to memory. Record, via 'primed' when
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// the memory is full.
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// the memory is full.
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dw_reset) // For simulation purposes, supply a valid value
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if (dw_reset) // For simulation purposes, supply a valid value
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begin
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begin
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waddr <= 0; // upon reset.
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waddr <= 0; // upon reset.
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dr_primed <= 1'b0;
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dr_primed <= 1'b0;
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end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
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end else if ((i_ce)&&((~dr_triggered)||(!dr_stopped)))
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begin
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begin
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// mem[waddr] <= i_data;
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// mem[waddr] <= i_data;
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waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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dr_primed <= (dr_primed)||(&waddr);
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dr_primed <= (dr_primed)||(&waddr);
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
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if ((i_ce)&&((~dr_triggered)||(!dr_stopped)))
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mem[waddr] <= i_data;
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mem[waddr] <= i_data;
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//
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//
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// Clock transfer of the status signals
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// Clock transfer of the status signals
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//
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//
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// Reads use the bus clock
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// Reads use the bus clock
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reg br_wb_ack;
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reg br_wb_ack;
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initial br_wb_ack = 1'b0;
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initial br_wb_ack = 1'b0;
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wire bw_cyc_stb;
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wire bw_cyc_stb;
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assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb));
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assign bw_cyc_stb = (i_wb_stb);
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
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begin
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if ((bw_reset_request)
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if ((bw_reset_request)
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||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
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||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
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raddr <= 0;
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raddr <= 0;
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