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// Filename: xioddr.v
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// Filename: xioddr.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose: For the DDR3 SDRAM, this handles the Xilinx specific portions
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// Purpose: For the DDR3 SDRAM, this handles the Xilinx specific portions
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// of the IO necessary to make this happen for one pin only.
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// of the IO necessary to make this happen for one pin only. (In
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// the end, this never worked for the DDR3 SDRAM ...) In the case of the
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// QSPI flash, this module helps to reduce the logic delays on the "high
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// speed" flash data wires (it's not really used in any DDR mode in that
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// case ...).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module xioddr(i_clk, i_oe, i_v, o_v, io_w);
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module xioddr(i_clk, i_oe, i_v, o_v, io_pin);
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input i_clk, i_oe;
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input i_clk, i_oe;
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input [1:0] i_v;
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input [1:0] i_v;
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output [1:0] o_v;
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output [1:0] o_v;
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inout io_w;
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inout io_pin;
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wire w_internal;
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wire w_internal;
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reg last;
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always @(posedge i_clk)
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last <= i_v[1];
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ODDR #(
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ODDR #(
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.DDR_CLK_EDGE("OPPOSITE_EDGE"),
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.DDR_CLK_EDGE("SAME_EDGE"),
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.INIT(1'b0),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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.SRTYPE("SYNC")
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) ODDRi(
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) ODDRi(
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.Q(w_internal),
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.Q(w_internal),
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.C(i_clk),
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.C(i_clk),
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.CE(1'b1),
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.CE(1'b1),
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.D1(i_v[0]),
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.D1(last), // Negative clock edge
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.D2(i_v[1]),
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.D2(i_v[0]), // Positive clock edge
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.R(1'b0),
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.R(1'b0),
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.S(1'b0));
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.S(1'b0));
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IDDR #(
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IDDR #(
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.DDR_CLK_EDGE("OPPOSITE_EDGE"),
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.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
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.INIT_Q1(1'b0),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q2(1'b0),
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.SRTYPE("SYNC")
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.SRTYPE("SYNC")
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) IDDRi(
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) IDDRi(
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.Q1(o_v[0]),
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.Q1(o_v[0]),
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.Q2(o_v[1]),
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.Q2(o_v[1]),
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.C(i_clk),
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.C(i_clk),
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.CE(1'b1),
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.CE(1'b1),
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.D(io_w),
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.D(io_pin),
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.R(1'b0),
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.R(1'b0),
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.S(1'b0));
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.S(1'b0));
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assign io_w = (i_oe) ? w_internal:1'bz;
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assign io_pin = (i_oe) ? w_internal:1'bz;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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