| Line 48... |
Line 48... |
//----------------------------------
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//----------------------------------
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//----Input
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//----Input
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//----------------------------------
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//----------------------------------
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input wire [FPW-1:0] tail ,
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input wire [FPW-1:0] tail ,
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input wire [(FPW*32)-1:0] d_in ,
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input wire [(FPW*32)-1:0] d_in ,
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input wire [FPW-1:0] valid ,
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//----------------------------------
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//----------------------------------
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//----Output
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//----Output
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//----------------------------------
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//----------------------------------
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output reg [31:0] crc_out
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output reg [31:0] crc_out
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| Line 74... |
Line 73... |
|
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`ifdef ASYNC_RES
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk) `endif
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always @(posedge clk) `endif
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begin
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begin
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`ifdef RESET_ALL
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if (!res_n) begin
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if (!res_n) begin
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crc_out <= 32'h0;
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crc_out <= 32'h0;
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crc_temp[0] <= 32'h0;
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end else
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end
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`endif
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else begin
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begin
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crc_out <= 32'h0;
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crc_out <= 32'h0;
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|
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for(i_f=0;i_f<FPW;i_f=i_f+1) begin
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for(i_f=0;i_f<FPW;i_f=i_f+1) begin
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if(tail[i_f]) begin
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if(tail[i_f]) begin
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crc_out <= crc_temp[i_f+1];
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crc_out <= crc_temp[i_f+1];
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end
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end
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end
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end
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|
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if(|tail) begin
|
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crc_temp[0] <= 32'h0;
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end else begin
|
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crc_temp[0] <= crc_temp[FPW];
|
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end
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end
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end
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end
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|
|
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
|
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always @(posedge clk) `endif
|
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begin
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if (!res_n)
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crc_temp[0] <= 32'h0;
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else
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crc_temp[0] <= |tail ? 32'h0 : crc_temp[FPW];
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end
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end
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|
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always @(*)
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always @(*)
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begin
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begin
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for(i_f=0;i_f<FPW;i_f=i_f+1) begin
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for(i_f=0;i_f<FPW;i_f=i_f+1) begin
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