OpenCores
URL https://opencores.org/ocsvn/openhmc/openhmc/trunk

Subversion Repositories openhmc

[/] [openhmc/] [trunk/] [openHMC/] [sim/] [tb/] [bfm/] [src/] [targets/] [dut_openhmc_behavioral_bfm.sv] - Diff between revs 12 and 15

Show entire file | Details | Blame | View Log

Rev 12 Rev 15
Line 71... Line 71...
wire [DWIDTH-1:0]       to_serializers;
wire [DWIDTH-1:0]       to_serializers;
wire [DWIDTH-1:0]       from_deserializers;
wire [DWIDTH-1:0]       from_deserializers;
wire [NUM_LANES-1:0]    bit_slip;
wire [NUM_LANES-1:0]    bit_slip;
wire [NUM_LANES-1:0]    phy_lane_polarity;
wire [NUM_LANES-1:0]    phy_lane_polarity;
bit                     P_RST_N;
bit                     P_RST_N;
 
//If transceiver models are used, clk_hmc should be sourced from the transceiver outclock and res_n hmc can be set independently
wire clk_hmc            = clk_user;
wire clk_hmc            = clk_user;
 
wire res_n_hmc          = res_n;
 
 
// Wire the HMC BFM model
// Wire the HMC BFM model
wire            LxRXPS; // HMC input
wire            LxRXPS; // HMC input
wire            LxTXPS; // HMC output
wire            LxTXPS; // HMC output
wire            FERR_N; // HMC output
wire            FERR_N; // HMC output
Line 94... Line 96...
assign serial_Rx    = LxTXP[NUM_LANES-1:0];
assign serial_Rx    = LxTXP[NUM_LANES-1:0];
assign serial_Txn = ~serial_Txp;
assign serial_Txn = ~serial_Txp;
 
 
//----------------------------- Attach the Register File System interface
//----------------------------- Attach the Register File System interface
assign rfs_hmc_if.clk = clk_hmc;
assign rfs_hmc_if.clk = clk_hmc;
assign rfs_hmc_if.res_n = res_n;
assign rfs_hmc_if.res_n = res_n_hmc;
 
 
 
//Assign the AXI4 IF
 
assign axi4_req.ACLK        = (`OPENHMC_ASYNC_FIFOS==0) ? clk_hmc : clk_user;
 
assign axi4_rsp.ACLK        = (`OPENHMC_ASYNC_FIFOS==0) ? clk_hmc : clk_user;
 
assign axi4_req.ARESET_N    = (`OPENHMC_ASYNC_FIFOS==0) ? res_n_hmc : res_n;
 
assign axi4_rsp.ARESET_N    = (`OPENHMC_ASYNC_FIFOS==0) ? res_n_hmc : res_n;
 
 
//----------------------------- Generate Clocks
//----------------------------- Generate Clocks
bit clk_10G;
bit clk_10G;
generate
generate
    begin : clocking_gen
    begin : clocking_gen
Line 106... Line 114...
        always #0.05ns clk_10G = ~clk_10G;
        always #0.05ns clk_10G = ~clk_10G;
    end
    end
endgenerate
endgenerate
 
 
//----------------------------- Behavioral SerDes
//----------------------------- Behavioral SerDes
 
bit LxTXPS_synced;
genvar lane;
genvar lane;
generate
generate
    begin : serializers_gen
    begin : serializers_gen
 
 
        for (lane=0; lane
        for (lane=0; lane
            serializer #(
            serializer #(
                .DWIDTH(LANE_WIDTH)
                .DWIDTH(LANE_WIDTH)
            ) serializer_I (
            ) serializer_I (
                .clk(clk_hmc),
                .clk(clk_hmc),
 
                .res_n(res_n),
                .fast_clk(clk_10G),
                .fast_clk(clk_10G),
                .data_in(to_serializers[lane*LANE_WIDTH+LANE_WIDTH-1:lane*LANE_WIDTH]),
                .data_in(to_serializers[lane*LANE_WIDTH+LANE_WIDTH-1:lane*LANE_WIDTH]),
                .data_out(serial_Txp[lane])
                .data_out(serial_Txp[lane])
            );
            );
            deserializer #(
            deserializer #(
                .DWIDTH(LANE_WIDTH)
                .DWIDTH(LANE_WIDTH)
            ) deserializer_I (
            ) deserializer_I (
                .clk(clk_hmc),
                .clk(clk_hmc),
 
                .res_n(LxTXPS_synced && res_n),
                .fast_clk(clk_10G),
                .fast_clk(clk_10G),
                .bit_slip(bit_slip[lane]),
                .bit_slip(bit_slip[lane]),
                .lane_polarity(phy_lane_polarity[lane]),
                .lane_polarity(phy_lane_polarity[lane]),
                .data_in(serial_Rx[lane]),
                .data_in(serial_Rx[lane]),
                .data_out(from_deserializers[lane*LANE_WIDTH+LANE_WIDTH-1:lane*LANE_WIDTH])
                .data_out(from_deserializers[lane*LANE_WIDTH+LANE_WIDTH-1:lane*LANE_WIDTH])
            );
            );
        end
        end
    end
    end
endgenerate
endgenerate
 
always @(posedge clk_hmc) LxTXPS_synced <= LxTXPS;
//=====================================================================================================
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//=====================================================================================================
openhmc_top #(
openhmc_top #(
    .LOG_FPW(LOG_FPW),
    .LOG_FPW(LOG_FPW),
    .FPW(FPW),
    .FPW(FPW),
    .LOG_NUM_LANES(LOG_NUM_LANES),
    .LOG_NUM_LANES(LOG_NUM_LANES),
    //Configure the Functionality
    //Configure the Functionality
    .LOG_MAX_RTC(10),                //That is max 1023 Tokens
    .LOG_MAX_RX_TOKENS(10),
 
    .LOG_MAX_HMC_TOKENS(10),                //That is max 1023 Tokens
    .HMC_RX_AC_COUPLED(1),
    .HMC_RX_AC_COUPLED(1),
    .CTRL_LANE_POLARITY(0),
    .CTRL_LANE_POLARITY(1),
    .CTRL_LANE_REVERSAL(1),
    .CTRL_LANE_REVERSAL(1),
    .BITSLIP_SHIFT_RIGHT(1),
    .BITSLIP_SHIFT_RIGHT(1),
 
    .OPEN_RSP_MODE(`OPEN_RSP_MODE),
 
    .SYNC_AXI4_IF(`OPENHMC_ASYNC_FIFOS==0),
    //Debug Logic
    //Debug Logic
    .DBG_RX_TOKEN_MON(1)    //Required by the test check sequence
    .DBG_RX_TOKEN_MON(1)    //Required by the test check sequence
 )
 )
openhmc_instance
openhmc_instance
 (
 (
Line 182... Line 196...
    //----Connect Physical Link
    //----Connect Physical Link
    //----------------------------------
    //----------------------------------
    .phy_data_tx_link2phy(to_serializers),
    .phy_data_tx_link2phy(to_serializers),
    .phy_data_rx_phy2link(from_deserializers),
    .phy_data_rx_phy2link(from_deserializers),
    .phy_bit_slip(bit_slip),
    .phy_bit_slip(bit_slip),
    .phy_ready(res_n),
    .phy_tx_ready(res_n),
 
    .phy_rx_ready(res_n),
    .phy_lane_polarity(phy_lane_polarity),
    .phy_lane_polarity(phy_lane_polarity),
 
    .phy_init_cont_set(),
 
 
    //----------------------------------
    //----------------------------------
    //----Connect HMC
    //----Connect HMC
    //----------------------------------
    //----------------------------------
    .P_RST_N(P_RST_N),
    .P_RST_N(P_RST_N),
    .hmc_LxRXPS(LxRXPS),
    .LXRXPS(LxRXPS),
    .hmc_LxTXPS(LxTXPS),
    .LXTXPS(LxTXPS),
    .FERR_N(FERR_N),
    .FERR_N(FERR_N),
 
 
    //----------------------------------
    //----------------------------------
    //----Connect RF
    //----Connect RF
    //----------------------------------
    //----------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.