| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 200 $
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// $Rev: 202 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2015-01-21 23:01:31 +0100 (Wed, 21 Jan 2015) $
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// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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| Line 66... |
Line 66... |
wire [15:0] per_din;
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wire [15:0] per_din;
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wire [15:0] per_dout;
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wire [15:0] per_dout;
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wire [1:0] per_we;
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wire [1:0] per_we;
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wire per_en;
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wire per_en;
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// Direct Memory Access interface
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wire [15:0] dma_dout;
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wire dma_ready;
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wire dma_resp;
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reg [15:1] dma_addr;
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reg [15:0] dma_din;
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reg dma_en;
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reg dma_priority;
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reg [1:0] dma_we;
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reg dma_wkup;
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// Digital I/O
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// Digital I/O
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wire irq_port1;
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wire irq_port1;
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wire irq_port2;
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wire irq_port2;
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wire [15:0] per_dout_dio;
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wire [15:0] per_dout_dio;
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wire [7:0] p1_dout;
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wire [7:0] p1_dout;
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| Line 190... |
Line 201... |
wire [15:0] inst_pc;
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wire [15:0] inst_pc;
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wire [8*32-1:0] inst_short;
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wire [8*32-1:0] inst_short;
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// Testbench variables
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// Testbench variables
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integer tb_idx;
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integer tb_idx;
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integer tmp_seed;
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integer error;
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integer error;
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reg stimulus_done;
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reg stimulus_done;
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//
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//
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| Line 205... |
Line 217... |
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// Debug interface tasks
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// Debug interface tasks
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`include "dbg_uart_tasks.v"
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`include "dbg_uart_tasks.v"
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`include "dbg_i2c_tasks.v"
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`include "dbg_i2c_tasks.v"
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// Direct Memory Access interface tasks
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`include "dma_tasks.v"
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// Verilog stimulus
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// Verilog stimulus
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`include "stimulus.v"
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`include "stimulus.v"
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//
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//
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| Line 263... |
Line 278... |
reset_n = 1'b1;
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reset_n = 1'b1;
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end
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end
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initial
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initial
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begin
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begin
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tmp_seed = `SEED;
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tmp_seed = $urandom(tmp_seed);
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error = 0;
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error = 0;
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stimulus_done = 1;
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stimulus_done = 1;
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irq = {`IRQ_NR-2{1'b0}};
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irq = {`IRQ_NR-2{1'b0}};
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nmi = 1'b0;
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nmi = 1'b0;
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wkup = 14'h0000;
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wkup = 14'h0000;
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dma_addr = 15'h0000;
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dma_din = 16'h0000;
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dma_en = 1'b0;
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dma_priority = 1'b0;
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dma_we = 2'b00;
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dma_wkup = 1'b0;
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dma_tfx_cancel = 1'b0;
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cpu_en = 1'b1;
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cpu_en = 1'b1;
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dbg_en = 1'b0;
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dbg_en = 1'b0;
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dbg_uart_rxd_sel = 1'b0;
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dbg_uart_rxd_sel = 1'b0;
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dbg_uart_rxd_dly = 1'b1;
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dbg_uart_rxd_dly = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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| Line 358... |
Line 382... |
.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
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.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
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.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_din (dmem_din), // Data Memory data input
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.dmem_din (dmem_din), // Data Memory data input
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.dmem_wen (dmem_wen), // Data Memory write byte enable (low active)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
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.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
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.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
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.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.dma_dout (dma_dout), // Direct Memory Access data output
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.dma_ready (dma_ready), // Direct Memory Access is complete
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.dma_resp (dma_resp), // Direct Memory Access response (0:Okay / 1:Error)
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_we (per_we), // Peripheral write enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write byte enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.pmem_wen (pmem_wen), // Program Memory write byte enable (low active) (optional)
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.puc_rst (puc_rst), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.smclk (smclk), // ASIC ONLY: SMCLK
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.smclk (smclk), // ASIC ONLY: SMCLK
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.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
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.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
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|
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// INPUTs
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// INPUTs
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| Line 387... |
Line 414... |
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_in), // Maskable interrupts
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.irq (irq_in), // Maskable interrupts
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.dma_addr (dma_addr), // Direct Memory Access address
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.dma_din (dma_din), // Direct Memory Access data input
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.dma_en (dma_en), // Direct Memory Access enable (high active)
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.dma_priority (dma_priority), // Direct Memory Access priority (0:low / 1:high)
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.dma_we (dma_we), // Direct Memory Access write byte enable (high active)
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.dma_wkup (dma_wkup), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.per_dout (per_dout), // Peripheral data output
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.per_dout (per_dout), // Peripheral data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.reset_n (reset_n), // Reset Pin (low active, asynchronous)
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.reset_n (reset_n), // Reset Pin (low active, asynchronous)
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.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
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.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
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| Line 492... |
Line 525... |
.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
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.ta_cci2a (ta_cci2a), // Timer A compare 2 input A
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.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
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.ta_cci2b (ta_cci2b), // Timer A compare 2 input B
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.taclk (taclk) // TACLK external timer clock (SLOW)
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.taclk (taclk) // TACLK external timer clock (SLOW)
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);
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);
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|
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//
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//
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// Peripheral templates
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// Peripheral templates
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//----------------------------------
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//----------------------------------
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|
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template_periph_8b template_periph_8b_0 (
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template_periph_8b template_periph_8b_0 (
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| Line 679... |
Line 711... |
`endif
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`endif
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION FAILED |");
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$display("| SIMULATION FAILED |");
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$display("| (simulation Timeout) |");
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$display("| (simulation Timeout) |");
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$display(" ===============================================");
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$display(" ===============================================");
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$display("");
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tb_extra_report;
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$finish;
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$finish;
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`endif
|
`endif
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end
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end
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|
|
initial // Normal end of test
|
initial // Normal end of test
|
begin
|
begin
|
@(negedge stimulus_done);
|
@(negedge stimulus_done);
|
wait(inst_pc=='hffff);
|
wait(inst_pc=='hffff);
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|
|
$display(" ===============================================");
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$display(" ===============================================");
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if (error!=0)
|
if ((dma_rd_error!=0) || (dma_wr_error!=0))
|
|
begin
|
|
$display("| SIMULATION FAILED |");
|
|
$display("| (some DMA transfer failed) |");
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|
end
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|
else if (error!=0)
|
begin
|
begin
|
$display("| SIMULATION FAILED |");
|
$display("| SIMULATION FAILED |");
|
$display("| (some verilog stimulus checks failed) |");
|
$display("| (some verilog stimulus checks failed) |");
|
end
|
end
|
else if (~stimulus_done)
|
else if (~stimulus_done)
|
| Line 704... |
Line 743... |
else
|
else
|
begin
|
begin
|
$display("| SIMULATION PASSED |");
|
$display("| SIMULATION PASSED |");
|
end
|
end
|
$display(" ===============================================");
|
$display(" ===============================================");
|
|
$display("");
|
|
tb_extra_report;
|
$finish;
|
$finish;
|
end
|
end
|
|
|
|
|
//
|
//
|
| Line 720... |
Line 761... |
$display("ERROR: %s %t", error_string, $time);
|
$display("ERROR: %s %t", error_string, $time);
|
error = error+1;
|
error = error+1;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
task tb_extra_report;
|
|
begin
|
|
$display("DMA REPORT: Total Accesses: %-d Total RD: %-d Total WR: %-d", dma_cnt_rd+dma_cnt_wr, dma_cnt_rd, dma_cnt_wr);
|
|
$display(" Total Errors: %-d Error RD: %-d Error WR: %-d", dma_rd_error+dma_wr_error, dma_rd_error, dma_wr_error);
|
|
if (!((`PMEM_SIZE>=4092) && (`DMEM_SIZE>=1024)))
|
|
begin
|
|
$display("");
|
|
$display("Note: DMA if verification disabled (PMEM must be 4kB or bigger, DMEM must be 1kB or bigger)");
|
|
end
|
|
$display("");
|
|
$display("SIMULATION SEED: %d", `SEED);
|
|
$display("");
|
|
end
|
|
endtask
|
|
|
|
task tb_skip_finish;
|
|
input [65*8-1:0] skip_string;
|
|
begin
|
|
$display(" ===============================================");
|
|
$display("| SIMULATION SKIPPED |");
|
|
$display("%s", skip_string);
|
|
$display(" ===============================================");
|
|
$display("");
|
|
tb_extra_report;
|
|
$finish;
|
|
end
|
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
