| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 180 $
|
// $Rev: 202 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
|
// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
| Line 49... |
Line 49... |
|
|
// OUTPUTs
|
// OUTPUTs
|
aclk, // ACLK
|
aclk, // ACLK
|
aclk_en, // ACLK enable
|
aclk_en, // ACLK enable
|
cpu_en_s, // Enable CPU code execution (synchronous)
|
cpu_en_s, // Enable CPU code execution (synchronous)
|
|
cpu_mclk, // Main system CPU only clock
|
|
dma_mclk, // Main system DMA and/or CPU clock
|
dbg_clk, // Debug unit clock
|
dbg_clk, // Debug unit clock
|
dbg_en_s, // Debug interface enable (synchronous)
|
dbg_en_s, // Debug interface enable (synchronous)
|
dbg_rst, // Debug unit reset
|
dbg_rst, // Debug unit reset
|
dco_enable, // Fast oscillator enable
|
dco_enable, // Fast oscillator enable
|
dco_wkup, // Fast oscillator wake-up (asynchronous)
|
dco_wkup, // Fast oscillator wake-up (asynchronous)
|
lfxt_enable, // Low frequency oscillator enable
|
lfxt_enable, // Low frequency oscillator enable
|
lfxt_wkup, // Low frequency oscillator wake-up (asynchronous)
|
lfxt_wkup, // Low frequency oscillator wake-up (asynchronous)
|
mclk, // Main system clock
|
|
per_dout, // Peripheral data output
|
per_dout, // Peripheral data output
|
por, // Power-on reset
|
por, // Power-on reset
|
puc_pnd_set, // PUC pending set for the serial debug interface
|
puc_pnd_set, // PUC pending set for the serial debug interface
|
puc_rst, // Main system reset
|
puc_rst, // Main system reset
|
smclk, // SMCLK
|
smclk, // SMCLK
|
| Line 71... |
Line 72... |
cpuoff, // Turns off the CPU
|
cpuoff, // Turns off the CPU
|
dbg_cpu_reset, // Reset CPU from debug interface
|
dbg_cpu_reset, // Reset CPU from debug interface
|
dbg_en, // Debug interface enable (asynchronous)
|
dbg_en, // Debug interface enable (asynchronous)
|
dco_clk, // Fast oscillator (fast clock)
|
dco_clk, // Fast oscillator (fast clock)
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
|
mclk_dma_enable, // DMA Sub-System Clock enable
|
|
mclk_dma_wkup, // DMA Sub-System Clock wake-up (asynchronous)
|
mclk_enable, // Main System Clock enable
|
mclk_enable, // Main System Clock enable
|
mclk_wkup, // Main System Clock wake-up (asynchronous)
|
mclk_wkup, // Main System Clock wake-up (asynchronous)
|
oscoff, // Turns off LFXT1 clock input
|
oscoff, // Turns off LFXT1 clock input
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
| Line 91... |
Line 94... |
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//=========
|
output aclk; // ACLK
|
output aclk; // ACLK
|
output aclk_en; // ACLK enable
|
output aclk_en; // ACLK enable
|
output cpu_en_s; // Enable CPU code execution (synchronous)
|
output cpu_en_s; // Enable CPU code execution (synchronous)
|
|
output cpu_mclk; // Main system CPU only clock
|
|
output dma_mclk; // Main system DMA and/or CPU clock
|
output dbg_clk; // Debug unit clock
|
output dbg_clk; // Debug unit clock
|
output dbg_en_s; // Debug unit enable (synchronous)
|
output dbg_en_s; // Debug unit enable (synchronous)
|
output dbg_rst; // Debug unit reset
|
output dbg_rst; // Debug unit reset
|
output dco_enable; // Fast oscillator enable
|
output dco_enable; // Fast oscillator enable
|
output dco_wkup; // Fast oscillator wake-up (asynchronous)
|
output dco_wkup; // Fast oscillator wake-up (asynchronous)
|
output lfxt_enable; // Low frequency oscillator enable
|
output lfxt_enable; // Low frequency oscillator enable
|
output lfxt_wkup; // Low frequency oscillator wake-up (asynchronous)
|
output lfxt_wkup; // Low frequency oscillator wake-up (asynchronous)
|
output mclk; // Main system clock
|
|
output [15:0] per_dout; // Peripheral data output
|
output [15:0] per_dout; // Peripheral data output
|
output por; // Power-on reset
|
output por; // Power-on reset
|
output puc_pnd_set; // PUC pending set for the serial debug interface
|
output puc_pnd_set; // PUC pending set for the serial debug interface
|
output puc_rst; // Main system reset
|
output puc_rst; // Main system reset
|
output smclk; // SMCLK
|
output smclk; // SMCLK
|
| Line 114... |
Line 118... |
input cpuoff; // Turns off the CPU
|
input cpuoff; // Turns off the CPU
|
input dbg_cpu_reset;// Reset CPU from debug interface
|
input dbg_cpu_reset;// Reset CPU from debug interface
|
input dbg_en; // Debug interface enable (asynchronous)
|
input dbg_en; // Debug interface enable (asynchronous)
|
input dco_clk; // Fast oscillator (fast clock)
|
input dco_clk; // Fast oscillator (fast clock)
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
|
input mclk_dma_enable; // DMA Sub-System Clock enable
|
|
input mclk_dma_wkup; // DMA Sub-System Clock wake-up (asynchronous)
|
input mclk_enable; // Main System Clock enable
|
input mclk_enable; // Main System Clock enable
|
input mclk_wkup; // Main System Clock wake-up (asynchronous)
|
input mclk_wkup; // Main System Clock wake-up (asynchronous)
|
input oscoff; // Turns off LFXT1 clock input
|
input oscoff; // Turns off LFXT1 clock input
|
input [13:0] per_addr; // Peripheral address
|
input [13:0] per_addr; // Peripheral address
|
input [15:0] per_din; // Peripheral data input
|
input [15:0] per_din; // Peripheral data input
|
| Line 198... |
Line 204... |
`ifdef ACLK_DIVIDER
|
`ifdef ACLK_DIVIDER
|
wire [7:0] divax_mask = 8'h30;
|
wire [7:0] divax_mask = 8'h30;
|
`else
|
`else
|
wire [7:0] divax_mask = 8'h00;
|
wire [7:0] divax_mask = 8'h00;
|
`endif
|
`endif
|
|
`ifdef DMA_IF_EN
|
|
`ifdef CPUOFF_EN
|
|
wire [7:0] dma_cpuoff_mask = 8'h01;
|
|
`else
|
|
wire [7:0] dma_cpuoff_mask = 8'h00;
|
|
`endif
|
|
`ifdef OSCOFF_EN
|
|
wire [7:0] dma_oscoff_mask = 8'h02;
|
|
`else
|
|
wire [7:0] dma_oscoff_mask = 8'h00;
|
|
`endif
|
|
`ifdef SCG0_EN
|
|
wire [7:0] dma_scg0_mask = 8'h04;
|
|
`else
|
|
wire [7:0] dma_scg0_mask = 8'h00;
|
|
`endif
|
|
`ifdef SCG1_EN
|
|
wire [7:0] dma_scg1_mask = 8'h08;
|
|
`else
|
|
wire [7:0] dma_scg1_mask = 8'h00;
|
|
`endif
|
|
`else
|
|
wire [7:0] dma_cpuoff_mask = 8'h00;
|
|
wire [7:0] dma_scg0_mask = 8'h00;
|
|
wire [7:0] dma_scg1_mask = 8'h00;
|
|
wire [7:0] dma_oscoff_mask = 8'h00;
|
|
`endif
|
`else
|
`else
|
wire [7:0] divax_mask = 8'h30;
|
wire [7:0] divax_mask = 8'h30;
|
|
wire [7:0] dma_cpuoff_mask = 8'h00;
|
|
wire [7:0] dma_scg0_mask = 8'h00;
|
|
`ifdef DMA_IF_EN
|
|
wire [7:0] dma_oscoff_mask = 8'h02;
|
|
wire [7:0] dma_scg1_mask = 8'h08;
|
|
`else
|
|
wire [7:0] dma_oscoff_mask = 8'h00;
|
|
wire [7:0] dma_scg1_mask = 8'h00;
|
|
`endif
|
`endif
|
`endif
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge dma_mclk or posedge puc_rst)
|
if (puc_rst) bcsctl1 <= 8'h00;
|
if (puc_rst) bcsctl1 <= 8'h00;
|
else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & divax_mask; // Mask unused bits
|
else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & (divax_mask |
|
|
dma_cpuoff_mask | dma_oscoff_mask |
|
|
dma_scg0_mask | dma_scg1_mask ); // Mask unused bits
|
|
|
|
|
// BCSCTL2 Register
|
// BCSCTL2 Register
|
//--------------
|
//--------------
|
reg [7:0] bcsctl2;
|
reg [7:0] bcsctl2;
|
| Line 239... |
Line 283... |
`else
|
`else
|
wire [7:0] sels_mask = 8'h08;
|
wire [7:0] sels_mask = 8'h08;
|
wire [7:0] divsx_mask = 8'h06;
|
wire [7:0] divsx_mask = 8'h06;
|
`endif
|
`endif
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge dma_mclk or posedge puc_rst)
|
if (puc_rst) bcsctl2 <= 8'h00;
|
if (puc_rst) bcsctl2 <= 8'h00;
|
else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & ( sels_mask | divsx_mask |
|
else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & ( sels_mask | divsx_mask |
|
selmx_mask | divmx_mask); // Mask unused bits
|
selmx_mask | divmx_mask); // Mask unused bits
|
|
|
|
|
| Line 263... |
Line 307... |
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
|
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
|
//=============================================================================
|
//=============================================================================
|
|
|
`ifdef ASIC_CLOCKING
|
`ifdef ASIC_CLOCKING
|
wire cpuoff_and_mclk_enable;
|
wire cpuoff_and_mclk_enable;
|
|
wire cpuoff_and_mclk_dma_enable;
|
|
wire cpuoff_and_mclk_dma_wkup;
|
|
`ifdef CPUOFF_EN
|
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
|
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
|
|
`ifdef DMA_IF_EN
|
|
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
|
|
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
|
|
`else
|
|
assign cpuoff_and_mclk_dma_enable = 1'b0;
|
|
assign cpuoff_and_mclk_dma_wkup = 1'b0;
|
|
`endif
|
|
`else
|
|
assign cpuoff_and_mclk_enable = 1'b0;
|
|
assign cpuoff_and_mclk_dma_enable = 1'b0;
|
|
assign cpuoff_and_mclk_dma_wkup = 1'b0;
|
|
wire UNUSED_cpuoff = cpuoff;
|
`endif
|
`endif
|
|
|
|
wire scg0_and_mclk_dma_enable;
|
|
wire scg0_and_mclk_dma_wkup;
|
|
`ifdef DMA_IF_EN
|
|
`ifdef SCG0_EN
|
|
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
|
|
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
|
|
`else
|
|
assign scg0_and_mclk_dma_enable = 1'b0;
|
|
assign scg0_and_mclk_dma_wkup = 1'b0;
|
|
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
|
|
`endif
|
|
`else
|
|
assign scg0_and_mclk_dma_enable = 1'b0;
|
|
assign scg0_and_mclk_dma_wkup = 1'b0;
|
|
`endif
|
|
|
|
wire scg1_and_mclk_dma_enable;
|
|
wire scg1_and_mclk_dma_wkup;
|
|
`ifdef DMA_IF_EN
|
|
`ifdef SCG1_EN
|
|
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
|
|
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
|
|
`else
|
|
assign scg1_and_mclk_dma_enable = 1'b0;
|
|
assign scg1_and_mclk_dma_wkup = 1'b0;
|
|
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
|
|
`endif
|
|
`else
|
|
assign scg1_and_mclk_dma_enable = 1'b0;
|
|
assign scg1_and_mclk_dma_wkup = 1'b0;
|
|
`endif
|
|
|
|
wire oscoff_and_mclk_dma_enable;
|
|
wire oscoff_and_mclk_dma_wkup;
|
|
`ifdef DMA_IF_EN
|
|
`ifdef OSCOFF_EN
|
|
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
|
|
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
|
|
`else
|
|
assign oscoff_and_mclk_dma_enable = 1'b0;
|
|
assign oscoff_and_mclk_dma_wkup = 1'b0;
|
|
wire UNUSED_oscoff_mclk_dma_wkup= mclk_dma_wkup;
|
|
`endif
|
|
`else
|
|
assign oscoff_and_mclk_dma_enable = 1'b0;
|
|
assign oscoff_and_mclk_dma_wkup = 1'b0;
|
|
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
|
|
`endif
|
|
`else
|
|
wire UNUSED_cpuoff = cpuoff;
|
|
wire UNUSED_mclk_enable = mclk_enable;
|
|
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
|
|
`endif
|
|
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// 5.1) HIGH SPEED SYSTEM CLOCK GENERATOR (DCO_CLK)
|
// 5.1) HIGH SPEED SYSTEM CLOCK GENERATOR (DCO_CLK)
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// Note1: switching off the DCO osillator is only
|
// Note1: switching off the DCO osillator is only
|
// supported in ASIC mode with SCG0 low power mode
|
// supported in ASIC mode with SCG0 low power mode
|
| Line 295... |
Line 409... |
wire dco_not_enabled_by_dbg;
|
wire dco_not_enabled_by_dbg;
|
wire dco_disable_by_scg0;
|
wire dco_disable_by_scg0;
|
wire dco_disable_by_cpu_en;
|
wire dco_disable_by_cpu_en;
|
wire dco_enable_nxt;
|
wire dco_enable_nxt;
|
omsp_and_gate and_dco_dis1 (.y(cpu_enabled_with_dco), .a(~bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
|
omsp_and_gate and_dco_dis1 (.y(cpu_enabled_with_dco), .a(~bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
|
omsp_and_gate and_dco_dis2 (.y(dco_not_enabled_by_dbg), .a(~dbg_en_s), .b(~cpu_enabled_with_dco));
|
omsp_and_gate and_dco_dis2 (.y(dco_not_enabled_by_dbg), .a(~dbg_en_s), .b(~(cpu_enabled_with_dco | scg0_and_mclk_dma_enable)));
|
omsp_and_gate and_dco_dis3 (.y(dco_disable_by_scg0), .a(scg0), .b(dco_not_enabled_by_dbg));
|
omsp_and_gate and_dco_dis3 (.y(dco_disable_by_scg0), .a(scg0), .b(dco_not_enabled_by_dbg));
|
omsp_and_gate and_dco_dis4 (.y(dco_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
|
omsp_and_gate and_dco_dis4 (.y(dco_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
|
omsp_and_gate and_dco_dis5 (.y(dco_enable_nxt), .a(~dco_disable_by_scg0), .b(~dco_disable_by_cpu_en));
|
omsp_and_gate and_dco_dis5 (.y(dco_enable_nxt), .a(~dco_disable_by_scg0), .b(~dco_disable_by_cpu_en));
|
|
|
// Register to prevent glitch propagation
|
// Register to prevent glitch propagation
|
| Line 316... |
Line 430... |
.data_in (~dco_disable),
|
.data_in (~dco_disable),
|
.clk (dco_clk_n),
|
.clk (dco_clk_n),
|
.rst (por)
|
.rst (por)
|
);
|
);
|
`else
|
`else
|
|
|
assign dco_enable = ~dco_disable;
|
assign dco_enable = ~dco_disable;
|
`endif
|
`endif
|
|
|
// The DCO oscillator will get an asynchronous wakeup if:
|
// The DCO oscillator will get an asynchronous wakeup if:
|
// - the MCLK generates a wakeup (only if the MCLK mux selects dco_clk)
|
// - the MCLK generates a wakeup (only if the MCLK mux selects dco_clk)
|
| Line 328... |
Line 441... |
wire dco_mclk_wkup;
|
wire dco_mclk_wkup;
|
wire dco_en_wkup;
|
wire dco_en_wkup;
|
omsp_and_gate and_dco_mclk_wkup (.y(dco_mclk_wkup), .a(mclk_wkup), .b(~bcsctl2[`SELMx]));
|
omsp_and_gate and_dco_mclk_wkup (.y(dco_mclk_wkup), .a(mclk_wkup), .b(~bcsctl2[`SELMx]));
|
omsp_and_gate and_dco_en_wkup (.y(dco_en_wkup), .a(~dco_enable), .b(dco_enable_nxt));
|
omsp_and_gate and_dco_en_wkup (.y(dco_en_wkup), .a(~dco_enable), .b(dco_enable_nxt));
|
|
|
wire dco_wkup_set = dco_mclk_wkup | dco_en_wkup | cpu_en_wkup;
|
wire dco_wkup_set = dco_mclk_wkup | scg0_and_mclk_dma_wkup | dco_en_wkup | cpu_en_wkup;
|
|
|
// Scan MUX for the asynchronous SET
|
// Scan MUX for the asynchronous SET
|
wire dco_wkup_set_scan;
|
wire dco_wkup_set_scan;
|
omsp_scan_mux scan_mux_dco_wkup (
|
omsp_scan_mux scan_mux_dco_wkup (
|
.scan_mode (scan_mode),
|
.scan_mode (scan_mode),
|
| Line 362... |
Line 475... |
omsp_and_gate and_dco_wkup (.y(dco_wkup), .a(~dco_wkup_n), .b(cpu_en));
|
omsp_and_gate and_dco_wkup (.y(dco_wkup), .a(~dco_wkup_n), .b(cpu_en));
|
|
|
`else
|
`else
|
assign dco_enable = 1'b1;
|
assign dco_enable = 1'b1;
|
assign dco_wkup = 1'b1;
|
assign dco_wkup = 1'b1;
|
|
wire UNUSED_scg0 = scg0;
|
|
wire UNUSED_cpu_en_wkup1 = cpu_en_wkup;
|
`endif
|
`endif
|
|
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// 5.2) LOW FREQUENCY CRYSTAL CLOCK GENERATOR (LFXT_CLK)
|
// 5.2) LOW FREQUENCY CRYSTAL CLOCK GENERATOR (LFXT_CLK)
|
| Line 388... |
Line 503... |
wire lfxt_not_enabled_by_dbg;
|
wire lfxt_not_enabled_by_dbg;
|
wire lfxt_disable_by_oscoff;
|
wire lfxt_disable_by_oscoff;
|
wire lfxt_disable_by_cpu_en;
|
wire lfxt_disable_by_cpu_en;
|
wire lfxt_enable_nxt;
|
wire lfxt_enable_nxt;
|
omsp_and_gate and_lfxt_dis1 (.y(cpu_enabled_with_lfxt), .a(bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
|
omsp_and_gate and_lfxt_dis1 (.y(cpu_enabled_with_lfxt), .a(bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
|
omsp_and_gate and_lfxt_dis2 (.y(lfxt_not_enabled_by_dbg), .a(~dbg_en_s), .b(~cpu_enabled_with_lfxt));
|
omsp_and_gate and_lfxt_dis2 (.y(lfxt_not_enabled_by_dbg), .a(~dbg_en_s), .b(~(cpu_enabled_with_lfxt | oscoff_and_mclk_dma_enable)));
|
omsp_and_gate and_lfxt_dis3 (.y(lfxt_disable_by_oscoff), .a(oscoff), .b(lfxt_not_enabled_by_dbg));
|
omsp_and_gate and_lfxt_dis3 (.y(lfxt_disable_by_oscoff), .a(oscoff), .b(lfxt_not_enabled_by_dbg));
|
omsp_and_gate and_lfxt_dis4 (.y(lfxt_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
|
omsp_and_gate and_lfxt_dis4 (.y(lfxt_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
|
omsp_and_gate and_lfxt_dis5 (.y(lfxt_enable_nxt), .a(~lfxt_disable_by_oscoff), .b(~lfxt_disable_by_cpu_en));
|
omsp_and_gate and_lfxt_dis5 (.y(lfxt_enable_nxt), .a(~lfxt_disable_by_oscoff), .b(~lfxt_disable_by_cpu_en));
|
|
|
// Register to prevent glitch propagation
|
// Register to prevent glitch propagation
|
| Line 416... |
Line 531... |
wire lfxt_mclk_wkup;
|
wire lfxt_mclk_wkup;
|
wire lfxt_en_wkup;
|
wire lfxt_en_wkup;
|
omsp_and_gate and_lfxt_mclk_wkup (.y(lfxt_mclk_wkup), .a(mclk_wkup), .b(bcsctl2[`SELMx]));
|
omsp_and_gate and_lfxt_mclk_wkup (.y(lfxt_mclk_wkup), .a(mclk_wkup), .b(bcsctl2[`SELMx]));
|
omsp_and_gate and_lfxt_en_wkup (.y(lfxt_en_wkup), .a(~lfxt_enable), .b(lfxt_enable_nxt));
|
omsp_and_gate and_lfxt_en_wkup (.y(lfxt_en_wkup), .a(~lfxt_enable), .b(lfxt_enable_nxt));
|
|
|
wire lfxt_wkup_set = lfxt_mclk_wkup | lfxt_en_wkup | cpu_en_wkup;
|
wire lfxt_wkup_set = lfxt_mclk_wkup | oscoff_and_mclk_dma_wkup | lfxt_en_wkup | cpu_en_wkup;
|
|
|
// Scan MUX for the asynchronous SET
|
// Scan MUX for the asynchronous SET
|
wire lfxt_wkup_set_scan;
|
wire lfxt_wkup_set_scan;
|
omsp_scan_mux scan_mux_lfxt_wkup (
|
omsp_scan_mux scan_mux_lfxt_wkup (
|
.scan_mode (scan_mode),
|
.scan_mode (scan_mode),
|
| Line 450... |
Line 565... |
omsp_and_gate and_lfxt_wkup (.y(lfxt_wkup), .a(~lfxt_wkup_n), .b(cpu_en));
|
omsp_and_gate and_lfxt_wkup (.y(lfxt_wkup), .a(~lfxt_wkup_n), .b(cpu_en));
|
|
|
`else
|
`else
|
assign lfxt_enable = 1'b1;
|
assign lfxt_enable = 1'b1;
|
assign lfxt_wkup = 1'b0;
|
assign lfxt_wkup = 1'b0;
|
|
wire UNUSED_oscoff = oscoff;
|
|
wire UNUSED_cpuoff_and_mclk_enable = cpuoff_and_mclk_enable;
|
|
wire UNUSED_cpu_en_wkup2 = cpu_en_wkup;
|
`endif
|
`endif
|
|
|
|
|
// FPGA MODE
|
// FPGA MODE
|
//---------------------------------------
|
//---------------------------------------
|
| Line 463... |
Line 581... |
wire lfxt_clk_s;
|
wire lfxt_clk_s;
|
|
|
omsp_sync_cell sync_cell_lfxt_clk (
|
omsp_sync_cell sync_cell_lfxt_clk (
|
.data_out (lfxt_clk_s),
|
.data_out (lfxt_clk_s),
|
.data_in (lfxt_clk),
|
.data_in (lfxt_clk),
|
.clk (mclk),
|
.clk (nodiv_mclk),
|
.rst (por)
|
.rst (por)
|
);
|
);
|
|
|
reg lfxt_clk_dly;
|
reg lfxt_clk_dly;
|
|
|
always @ (posedge mclk or posedge por)
|
always @ (posedge nodiv_mclk or posedge por)
|
if (por) lfxt_clk_dly <= 1'b0;
|
if (por) lfxt_clk_dly <= 1'b0;
|
else lfxt_clk_dly <= lfxt_clk_s;
|
else lfxt_clk_dly <= lfxt_clk_s;
|
|
|
wire lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & ~(oscoff & ~bcsctl2[`SELS]);
|
wire lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & (~oscoff | (mclk_dma_enable & bcsctl1[`DMA_OSCOFF]));
|
assign lfxt_enable = 1'b1;
|
assign lfxt_enable = 1'b1;
|
assign lfxt_wkup = 1'b0;
|
assign lfxt_wkup = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
| Line 485... |
Line 603... |
// 6) CLOCK GENERATION
|
// 6) CLOCK GENERATION
|
//=============================================================================
|
//=============================================================================
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// 6.1) GLOBAL CPU ENABLE
|
// 6.1) GLOBAL CPU ENABLE
|
//-----------------------------------------------------------
|
//----------------------------------------------------------
|
// ACLK and SMCLK are directly switched-off
|
// ACLK and SMCLK are directly switched-off
|
// with the cpu_en pin (after synchronization).
|
// with the cpu_en pin (after synchronization).
|
// MCLK will be switched off once the CPU reaches
|
// MCLK will be switched off once the CPU reaches
|
// its IDLE state (through the mclk_enable signal)
|
// its IDLE state (through the mclk_enable signal)
|
|
|
| Line 552... |
Line 670... |
.clk_out (nodiv_mclk),
|
.clk_out (nodiv_mclk),
|
.clk_in0 (dco_clk),
|
.clk_in0 (dco_clk),
|
.clk_in1 (lfxt_clk),
|
.clk_in1 (lfxt_clk),
|
.reset (por),
|
.reset (por),
|
.scan_mode (scan_mode),
|
.scan_mode (scan_mode),
|
.select (bcsctl2[`SELMx])
|
.select_in (bcsctl2[`SELMx])
|
);
|
);
|
`else
|
`else
|
assign nodiv_mclk = dco_clk;
|
assign nodiv_mclk = dco_clk;
|
`endif
|
`endif
|
assign nodiv_mclk_n = ~nodiv_mclk;
|
assign nodiv_mclk_n = ~nodiv_mclk;
|
|
|
|
|
// Wakeup synchronizer
|
// Wakeup synchronizer
|
//----------------------------
|
//----------------------------
|
|
wire cpuoff_and_mclk_dma_wkup_s;
|
wire mclk_wkup_s;
|
wire mclk_wkup_s;
|
|
|
`ifdef CPUOFF_EN
|
`ifdef CPUOFF_EN
|
|
`ifdef DMA_IF_EN
|
|
omsp_sync_cell sync_cell_mclk_dma_wkup (
|
|
.data_out (cpuoff_and_mclk_dma_wkup_s),
|
|
.data_in (cpuoff_and_mclk_dma_wkup),
|
|
.clk (nodiv_mclk),
|
|
.rst (puc_rst)
|
|
);
|
|
`else
|
|
assign cpuoff_and_mclk_dma_wkup_s = 1'b0;
|
|
`endif
|
omsp_sync_cell sync_cell_mclk_wkup (
|
omsp_sync_cell sync_cell_mclk_wkup (
|
.data_out (mclk_wkup_s),
|
.data_out (mclk_wkup_s),
|
.data_in (mclk_wkup),
|
.data_in (mclk_wkup),
|
.clk (nodiv_mclk),
|
.clk (nodiv_mclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
);
|
);
|
`else
|
`else
|
|
assign cpuoff_and_mclk_dma_wkup_s = 1'b0;
|
assign mclk_wkup_s = 1'b0;
|
assign mclk_wkup_s = 1'b0;
|
|
wire UNUSED_mclk_wkup = mclk_wkup;
|
`endif
|
`endif
|
|
|
|
|
// Clock Divider
|
// Clock Divider
|
//----------------------------
|
//----------------------------
|
// No need for extra synchronizer as bcsctl2
|
// No need for extra synchronizer as bcsctl2
|
// comes from the same clock domain.
|
// comes from the same clock domain.
|
|
|
`ifdef CPUOFF_EN
|
`ifdef CPUOFF_EN
|
wire mclk_active = mclk_enable | mclk_wkup_s | (dbg_en_s & cpu_en_s);
|
wire mclk_active = mclk_enable | mclk_wkup_s | (dbg_en_s & cpu_en_s);
|
|
wire mclk_dma_active = cpuoff_and_mclk_dma_enable | cpuoff_and_mclk_dma_wkup_s | mclk_active;
|
`else
|
`else
|
wire mclk_active = 1'b1;
|
wire mclk_active = 1'b1;
|
|
wire mclk_dma_active = 1'b1;
|
`endif
|
`endif
|
|
|
`ifdef MCLK_DIVIDER
|
`ifdef MCLK_DIVIDER
|
reg [2:0] mclk_div;
|
reg [2:0] mclk_div;
|
always @ (posedge nodiv_mclk or posedge puc_rst)
|
always @ (posedge nodiv_mclk or posedge puc_rst)
|
if (puc_rst) mclk_div <= 3'h0;
|
if (puc_rst) mclk_div <= 3'h0;
|
else if ((bcsctl2[`DIVMx]!=2'b00)) mclk_div <= mclk_div+3'h1;
|
else if ((bcsctl2[`DIVMx]!=2'b00)) mclk_div <= mclk_div+3'h1;
|
|
|
wire mclk_div_en = mclk_active & ((bcsctl2[`DIVMx]==2'b00) ? 1'b1 :
|
wire mclk_div_sel = (bcsctl2[`DIVMx]==2'b00) ? 1'b1 :
|
(bcsctl2[`DIVMx]==2'b01) ? mclk_div[0] :
|
(bcsctl2[`DIVMx]==2'b01) ? mclk_div[0] :
|
(bcsctl2[`DIVMx]==2'b10) ? &mclk_div[1:0] :
|
(bcsctl2[`DIVMx]==2'b10) ? &mclk_div[1:0] :
|
&mclk_div[2:0]);
|
&mclk_div[2:0] ;
|
|
|
|
wire mclk_div_en = mclk_active & mclk_div_sel;
|
|
wire mclk_dma_div_en = mclk_dma_active & mclk_div_sel;
|
|
|
`else
|
`else
|
wire mclk_div_en = mclk_active;
|
wire mclk_div_en = mclk_active;
|
|
wire mclk_dma_div_en = mclk_dma_active;
|
`endif
|
`endif
|
|
|
|
|
// Generate main system clock
|
// Generate main system clock
|
//----------------------------
|
//----------------------------
|
`ifdef MCLK_CGATE
|
`ifdef MCLK_CGATE
|
|
|
omsp_clock_gate clock_gate_mclk (
|
omsp_clock_gate clock_gate_mclk (
|
.gclk (mclk),
|
.gclk (cpu_mclk),
|
.clk (nodiv_mclk),
|
.clk (nodiv_mclk),
|
.enable (mclk_div_en),
|
.enable (mclk_div_en),
|
.scan_enable (scan_enable)
|
.scan_enable (scan_enable)
|
);
|
);
|
|
`ifdef DMA_IF_EN
|
|
omsp_clock_gate clock_gate_dma_mclk (
|
|
.gclk (dma_mclk),
|
|
.clk (nodiv_mclk),
|
|
.enable (mclk_dma_div_en),
|
|
.scan_enable (scan_enable)
|
|
);
|
`else
|
`else
|
assign mclk = nodiv_mclk;
|
assign dma_mclk = cpu_mclk;
|
|
`endif
|
|
`else
|
|
assign cpu_mclk = nodiv_mclk;
|
|
assign dma_mclk = nodiv_mclk;
|
`endif
|
`endif
|
|
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// 6.3) ACLK GENERATION
|
// 6.3) ACLK GENERATION
|
| Line 630... |
Line 779... |
`ifdef ACLK_DIVIDER
|
`ifdef ACLK_DIVIDER
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
|
|
wire nodiv_aclk = lfxt_clk;
|
wire nodiv_aclk = lfxt_clk;
|
|
|
|
// Synchronizers
|
|
//------------------------------------------------------
|
|
|
// Local Reset synchronizer
|
// Local Reset synchronizer
|
wire puc_lfxt_rst;
|
|
wire puc_lfxt_noscan_n;
|
wire puc_lfxt_noscan_n;
|
|
wire puc_lfxt_rst;
|
omsp_sync_cell sync_cell_puc_lfxt (
|
omsp_sync_cell sync_cell_puc_lfxt (
|
.data_out (puc_lfxt_noscan_n),
|
.data_out (puc_lfxt_noscan_n),
|
.data_in (1'b1),
|
.data_in (1'b1),
|
.clk (nodiv_aclk),
|
.clk (nodiv_aclk),
|
.rst (puc_rst)
|
.rst (puc_rst)
|
| Line 646... |
Line 798... |
.data_in_scan (por_a),
|
.data_in_scan (por_a),
|
.data_in_func (~puc_lfxt_noscan_n),
|
.data_in_func (~puc_lfxt_noscan_n),
|
.data_out (puc_lfxt_rst)
|
.data_out (puc_lfxt_rst)
|
);
|
);
|
|
|
|
// If the OSCOFF mode is enabled synchronize OSCOFF signal
|
|
wire oscoff_s;
|
|
`ifdef OSCOFF_EN
|
|
omsp_sync_cell sync_cell_oscoff (
|
|
.data_out (oscoff_s),
|
|
.data_in (oscoff),
|
|
.clk (nodiv_aclk),
|
|
.rst (puc_lfxt_rst)
|
|
);
|
|
`else
|
|
assign oscoff_s = 1'b0;
|
|
`endif
|
|
|
// Local synchronizer for the bcsctl1.DIVAx configuration
|
// Local synchronizer for the bcsctl1.DIVAx configuration
|
// (note that we can live with a full bus synchronizer as
|
// (note that we can live with a full bus synchronizer as
|
// it won't hurt if we get a wrong DIVAx value for a single clock cycle)
|
// it won't hurt if we get a wrong DIVAx value for a single clock cycle)
|
reg [1:0] divax_s;
|
reg [1:0] divax_s;
|
reg [1:0] divax_ss;
|
reg [1:0] divax_ss;
|
| Line 663... |
Line 828... |
begin
|
begin
|
divax_s <= bcsctl1[`DIVAx];
|
divax_s <= bcsctl1[`DIVAx];
|
divax_ss <= divax_s;
|
divax_ss <= divax_s;
|
end
|
end
|
|
|
// If the OSCOFF mode is enabled synchronize OSCOFF signal
|
`else
|
wire oscoff_s;
|
wire puc_lfxt_rst = puc_rst;
|
|
wire nodiv_aclk = dco_clk;
|
|
wire [1:0] divax_ss = bcsctl1[`DIVAx];
|
|
wire oscoff_s = oscoff;
|
|
`endif
|
|
|
|
// Wakeup synchronizer
|
|
//----------------------------
|
|
wire oscoff_and_mclk_dma_enable_s;
|
|
|
`ifdef OSCOFF_EN
|
`ifdef OSCOFF_EN
|
omsp_sync_cell sync_cell_oscoff (
|
`ifdef DMA_IF_EN
|
.data_out (oscoff_s),
|
omsp_sync_cell sync_cell_aclk_dma_wkup (
|
.data_in (oscoff),
|
.data_out (oscoff_and_mclk_dma_enable_s),
|
|
.data_in (oscoff_and_mclk_dma_wkup | oscoff_and_mclk_dma_enable),
|
.clk (nodiv_aclk),
|
.clk (nodiv_aclk),
|
.rst (puc_lfxt_rst)
|
.rst (puc_lfxt_rst)
|
);
|
);
|
`else
|
`else
|
assign oscoff_s = 1'b0;
|
assign oscoff_and_mclk_dma_enable_s = 1'b0;
|
`endif
|
`endif
|
`else
|
`else
|
wire puc_lfxt_rst = puc_rst;
|
assign oscoff_and_mclk_dma_enable_s = 1'b0;
|
wire nodiv_aclk = dco_clk;
|
|
wire [1:0] divax_ss = bcsctl1[`DIVAx];
|
|
wire oscoff_s = oscoff;
|
|
`endif
|
`endif
|
|
|
// Divider
|
// Clock Divider
|
|
//----------------------------
|
|
|
|
wire aclk_active = cpu_en_aux_s & (~oscoff_s | oscoff_and_mclk_dma_enable_s);
|
|
|
reg [2:0] aclk_div;
|
reg [2:0] aclk_div;
|
always @ (posedge nodiv_aclk or posedge puc_lfxt_rst)
|
always @ (posedge nodiv_aclk or posedge puc_lfxt_rst)
|
if (puc_lfxt_rst) aclk_div <= 3'h0;
|
if (puc_lfxt_rst) aclk_div <= 3'h0;
|
else if ((divax_ss!=2'b00)) aclk_div <= aclk_div+3'h1;
|
else if ((divax_ss!=2'b00)) aclk_div <= aclk_div+3'h1;
|
|
|
wire aclk_div_en = cpu_en_aux_s & ~oscoff_s & ((divax_ss==2'b00) ? 1'b1 :
|
wire aclk_div_sel = ((divax_ss==2'b00) ? 1'b1 :
|
(divax_ss==2'b01) ? aclk_div[0] :
|
(divax_ss==2'b01) ? aclk_div[0] :
|
(divax_ss==2'b10) ? &aclk_div[1:0] :
|
(divax_ss==2'b10) ? &aclk_div[1:0] :
|
&aclk_div[2:0]);
|
&aclk_div[2:0]);
|
|
|
|
wire aclk_div_en = aclk_active & aclk_div_sel;
|
|
|
// Clock gate
|
// Clock gate
|
omsp_clock_gate clock_gate_aclk (
|
omsp_clock_gate clock_gate_aclk (
|
.gclk (aclk),
|
.gclk (aclk),
|
.clk (nodiv_aclk),
|
.clk (nodiv_aclk),
|
.enable (aclk_div_en),
|
.enable (aclk_div_en),
|
| Line 707... |
Line 885... |
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
assign aclk = lfxt_clk;
|
assign aclk = lfxt_clk;
|
`else
|
`else
|
assign aclk = dco_clk;
|
assign aclk = dco_clk;
|
`endif
|
`endif
|
|
wire UNUSED_cpu_en_aux_s = cpu_en_aux_s;
|
`endif
|
`endif
|
|
|
|
`ifdef LFXT_DOMAIN
|
|
`else
|
|
wire UNUSED_lfxt_clk = lfxt_clk;
|
|
`endif
|
|
|
assign aclk_en = 1'b1;
|
assign aclk_en = 1'b1;
|
|
|
|
|
// FPGA MODE
|
// FPGA MODE
|
| Line 723... |
Line 906... |
wire aclk_en_nxt = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
|
wire aclk_en_nxt = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
|
(bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
|
(bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
|
(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
|
(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
|
&aclk_div[2:0]);
|
&aclk_div[2:0]);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge nodiv_mclk or posedge puc_rst)
|
if (puc_rst) aclk_div <= 3'h0;
|
if (puc_rst) aclk_div <= 3'h0;
|
else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
|
else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge nodiv_mclk or posedge puc_rst)
|
if (puc_rst) aclk_en <= 1'b0;
|
if (puc_rst) aclk_en <= 1'b0;
|
else aclk_en <= aclk_en_nxt & cpu_en_s;
|
else aclk_en <= aclk_en_nxt & cpu_en_s;
|
|
|
assign aclk = mclk;
|
assign aclk = nodiv_mclk;
|
|
|
|
wire UNUSED_scan_enable = scan_enable;
|
|
wire UNUSED_scan_mode = scan_mode;
|
`endif
|
`endif
|
|
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// 6.4) SMCLK GENERATION
|
// 6.4) SMCLK GENERATION
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
// Clock MUX
|
// Clock MUX
|
| Line 747... |
Line 934... |
.clk_out (nodiv_smclk),
|
.clk_out (nodiv_smclk),
|
.clk_in0 (dco_clk),
|
.clk_in0 (dco_clk),
|
.clk_in1 (lfxt_clk),
|
.clk_in1 (lfxt_clk),
|
.reset (por),
|
.reset (por),
|
.scan_mode (scan_mode),
|
.scan_mode (scan_mode),
|
.select (bcsctl2[`SELS])
|
.select_in (bcsctl2[`SELS])
|
);
|
);
|
`else
|
`else
|
assign nodiv_smclk = dco_clk;
|
assign nodiv_smclk = dco_clk;
|
`endif
|
`endif
|
|
|
| Line 759... |
Line 946... |
// ASIC MODE
|
// ASIC MODE
|
//----------------------------
|
//----------------------------
|
`ifdef ASIC_CLOCKING
|
`ifdef ASIC_CLOCKING
|
`ifdef SMCLK_MUX
|
`ifdef SMCLK_MUX
|
|
|
// Synchronizers
|
// SMCLK_MUX Synchronizers
|
//------------------------------------------------------
|
//------------------------------------------------------
|
// When the SMCLK MUX is enabled, the reset and DIVSx
|
// When the SMCLK MUX is enabled, the reset and DIVSx
|
// and SCG1 signals must be synchronized, otherwise not.
|
// and SCG1 signals must be synchronized, otherwise not.
|
|
|
// Local Reset synchronizer
|
// Local Reset synchronizer
|
| Line 781... |
Line 968... |
.data_in_func (~puc_sm_noscan_n),
|
.data_in_func (~puc_sm_noscan_n),
|
.data_out (puc_sm_rst)
|
.data_out (puc_sm_rst)
|
);
|
);
|
|
|
// SCG1 synchronizer
|
// SCG1 synchronizer
|
`ifdef SCG1_EN
|
|
wire scg1_s;
|
wire scg1_s;
|
|
`ifdef SCG1_EN
|
omsp_sync_cell sync_cell_scg1 (
|
omsp_sync_cell sync_cell_scg1 (
|
.data_out (scg1_s),
|
.data_out (scg1_s),
|
.data_in (scg1),
|
.data_in (scg1),
|
.clk (nodiv_smclk),
|
.clk (nodiv_smclk),
|
.rst (puc_sm_rst)
|
.rst (puc_sm_rst)
|
);
|
);
|
`else
|
`else
|
wire scg1_s = 1'b0;
|
assign scg1_s = 1'b0;
|
|
wire UNUSED_scg1 = scg1;
|
|
wire UNUSED_puc_sm_rst = puc_sm_rst;
|
`endif
|
`endif
|
|
|
`ifdef SMCLK_DIVIDER
|
`ifdef SMCLK_DIVIDER
|
// Local synchronizer for the bcsctl2.DIVSx configuration
|
// Local synchronizer for the bcsctl2.DIVSx configuration
|
// (note that we can live with a full bus synchronizer as
|
// (note that we can live with a full bus synchronizer as
|
| Line 819... |
Line 1008... |
wire puc_sm_rst = puc_rst;
|
wire puc_sm_rst = puc_rst;
|
wire [1:0] divsx_ss = bcsctl2[`DIVSx];
|
wire [1:0] divsx_ss = bcsctl2[`DIVSx];
|
wire scg1_s = scg1;
|
wire scg1_s = scg1;
|
`endif
|
`endif
|
|
|
|
// Wakeup synchronizer
|
|
//----------------------------
|
|
wire scg1_and_mclk_dma_enable_s;
|
|
|
|
`ifdef SCG1_EN
|
|
`ifdef DMA_IF_EN
|
|
`ifdef SMCLK_MUX
|
|
omsp_sync_cell sync_cell_smclk_dma_wkup (
|
|
.data_out (scg1_and_mclk_dma_enable_s),
|
|
.data_in (scg1_and_mclk_dma_wkup | scg1_and_mclk_dma_enable),
|
|
.clk (nodiv_smclk),
|
|
.rst (puc_sm_rst)
|
|
);
|
|
`else
|
|
wire scg1_and_mclk_dma_wkup_s;
|
|
omsp_sync_cell sync_cell_smclk_dma_wkup (
|
|
.data_out (scg1_and_mclk_dma_wkup_s),
|
|
.data_in (scg1_and_mclk_dma_wkup),
|
|
.clk (nodiv_smclk),
|
|
.rst (puc_sm_rst)
|
|
);
|
|
assign scg1_and_mclk_dma_enable_s = scg1_and_mclk_dma_wkup_s | scg1_and_mclk_dma_enable;
|
|
`endif
|
|
`else
|
|
assign scg1_and_mclk_dma_enable_s = 1'b0;
|
|
`endif
|
|
`else
|
|
assign scg1_and_mclk_dma_enable_s = 1'b0;
|
|
`endif
|
|
|
|
|
// Clock Divider
|
// Clock Divider
|
//----------------------------
|
//----------------------------
|
`ifdef SMCLK_DIVIDER
|
`ifdef SCG1_EN
|
|
wire smclk_active = cpu_en_sm_s & (~scg1_s | scg1_and_mclk_dma_enable_s);
|
|
`else
|
|
wire smclk_active = cpu_en_sm_s;
|
|
`endif
|
|
|
|
`ifdef SMCLK_DIVIDER
|
reg [2:0] smclk_div;
|
reg [2:0] smclk_div;
|
always @ (posedge nodiv_smclk or posedge puc_sm_rst)
|
always @ (posedge nodiv_smclk or posedge puc_sm_rst)
|
if (puc_sm_rst) smclk_div <= 3'h0;
|
if (puc_sm_rst) smclk_div <= 3'h0;
|
else if ((divsx_ss!=2'b00)) smclk_div <= smclk_div+3'h1;
|
else if ((divsx_ss!=2'b00)) smclk_div <= smclk_div+3'h1;
|
|
|
wire smclk_div_en = cpu_en_sm_s & ~scg1_s & ((divsx_ss==2'b00) ? 1'b1 :
|
wire smclk_div_sel = ((divsx_ss==2'b00) ? 1'b1 :
|
(divsx_ss==2'b01) ? smclk_div[0] :
|
(divsx_ss==2'b01) ? smclk_div[0] :
|
(divsx_ss==2'b10) ? &smclk_div[1:0] :
|
(divsx_ss==2'b10) ? &smclk_div[1:0] :
|
&smclk_div[2:0]);
|
&smclk_div[2:0]);
|
|
|
|
wire smclk_div_en = smclk_active & smclk_div_sel;
|
`else
|
`else
|
`ifdef SCG1_EN
|
wire smclk_div_en = smclk_active;
|
wire smclk_div_en = cpu_en_sm_s & ~scg1_s;
|
|
`else
|
|
wire smclk_div_en = cpu_en_sm_s;
|
|
`endif
|
|
`endif
|
`endif
|
|
|
|
|
// Generate sub-system clock
|
// Generate sub-system clock
|
//----------------------------
|
//----------------------------
|
| Line 865... |
Line 1086... |
//----------------------------
|
//----------------------------
|
`else
|
`else
|
reg smclk_en;
|
reg smclk_en;
|
reg [2:0] smclk_div;
|
reg [2:0] smclk_div;
|
|
|
wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1);
|
wire smclk_in = (scg1 & ~(mclk_dma_enable & bcsctl1[`DMA_SCG1])) ? 1'b0 :
|
|
bcsctl2[`SELS] ? lfxt_clk_en : 1'b1;
|
|
|
wire smclk_en_nxt = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
|
wire smclk_en_nxt = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
|
(bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
|
(bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
|
(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
|
(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
|
&smclk_div[2:0]);
|
&smclk_div[2:0]);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge nodiv_mclk or posedge puc_rst)
|
if (puc_rst) smclk_en <= 1'b0;
|
if (puc_rst) smclk_en <= 1'b0;
|
else smclk_en <= smclk_en_nxt & cpu_en_s;
|
else smclk_en <= smclk_en_nxt & cpu_en_s;
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge nodiv_mclk or posedge puc_rst)
|
if (puc_rst) smclk_div <= 3'h0;
|
if (puc_rst) smclk_div <= 3'h0;
|
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
|
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
|
|
|
wire smclk = mclk;
|
wire smclk = nodiv_mclk;
|
|
|
`endif
|
`endif
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
// 6.5) DEBUG INTERFACE CLOCK GENERATION (DBG_CLK)
|
// 6.5) DEBUG INTERFACE CLOCK GENERATION (DBG_CLK)
|
| Line 896... |
Line 1118... |
`ifdef SYNC_DBG_EN
|
`ifdef SYNC_DBG_EN
|
wire dbg_en_n_s;
|
wire dbg_en_n_s;
|
omsp_sync_cell sync_cell_dbg_en (
|
omsp_sync_cell sync_cell_dbg_en (
|
.data_out (dbg_en_n_s),
|
.data_out (dbg_en_n_s),
|
.data_in (~dbg_en),
|
.data_in (~dbg_en),
|
.clk (mclk),
|
.clk (cpu_mclk),
|
.rst (por)
|
.rst (por)
|
);
|
);
|
assign dbg_en_s = ~dbg_en_n_s;
|
assign dbg_en_s = ~dbg_en_n_s;
|
wire dbg_rst_nxt = dbg_en_n_s;
|
wire dbg_rst_nxt = dbg_en_n_s;
|
`else
|
`else
|
| Line 908... |
Line 1130... |
wire dbg_rst_nxt = ~dbg_en;
|
wire dbg_rst_nxt = ~dbg_en;
|
`endif
|
`endif
|
`else
|
`else
|
assign dbg_en_s = 1'b0;
|
assign dbg_en_s = 1'b0;
|
wire dbg_rst_nxt = 1'b0;
|
wire dbg_rst_nxt = 1'b0;
|
|
wire UNUSED_dbg_en = dbg_en;
|
`endif
|
`endif
|
|
|
|
|
|
|
// Serial Debug Interface Clock gate
|
// Serial Debug Interface Clock gate
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef DBG_EN
|
`ifdef DBG_EN
|
`ifdef ASIC_CLOCKING
|
`ifdef ASIC_CLOCKING
|
omsp_clock_gate clock_gate_dbg_clk (
|
omsp_clock_gate clock_gate_dbg_clk (
|
.gclk (dbg_clk),
|
.gclk (dbg_clk),
|
.clk (mclk),
|
.clk (cpu_mclk),
|
.enable (dbg_en_s),
|
.enable (dbg_en_s),
|
.scan_enable (scan_enable)
|
.scan_enable (scan_enable)
|
);
|
);
|
`else
|
`else
|
assign dbg_clk = dco_clk;
|
assign dbg_clk = dco_clk;
|
| Line 975... |
Line 1199... |
//------------------------------------------
|
//------------------------------------------
|
`ifdef DBG_EN
|
`ifdef DBG_EN
|
|
|
// Reset Generation
|
// Reset Generation
|
reg dbg_rst_noscan;
|
reg dbg_rst_noscan;
|
always @ (posedge mclk or posedge por)
|
always @ (posedge cpu_mclk or posedge por)
|
if (por) dbg_rst_noscan <= 1'b1;
|
if (por) dbg_rst_noscan <= 1'b1;
|
else dbg_rst_noscan <= dbg_rst_nxt;
|
else dbg_rst_noscan <= dbg_rst_nxt;
|
|
|
// Scan Reset Mux
|
// Scan Reset Mux
|
`ifdef ASIC
|
`ifdef ASIC
|
| Line 1028... |
Line 1252... |
// Reset Synchronizer
|
// Reset Synchronizer
|
// (required because of the asynchronous watchdog reset)
|
// (required because of the asynchronous watchdog reset)
|
omsp_sync_cell sync_cell_puc (
|
omsp_sync_cell sync_cell_puc (
|
.data_out (puc_noscan_n),
|
.data_out (puc_noscan_n),
|
.data_in (~puc_s),
|
.data_in (~puc_s),
|
.clk (mclk),
|
.clk (cpu_mclk),
|
.rst (puc_a_scan)
|
.rst (puc_a_scan)
|
);
|
);
|
|
|
// Scan Reset Mux
|
// Scan Reset Mux
|
`ifdef ASIC
|
`ifdef ASIC
|
