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Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 175 $
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// $Rev: 202 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $
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// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 488... |
Line 488... |
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`else
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`else
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assign brk0_halt = 1'b0;
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assign brk0_halt = 1'b0;
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assign brk0_pnd = 1'b0;
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assign brk0_pnd = 1'b0;
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assign brk0_dout = 16'h0000;
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assign brk0_dout = 16'h0000;
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wire [15:0] UNUSED_eu_mab = eu_mab;
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wire UNUSED_eu_mb_en = eu_mb_en;
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wire [1:0] UNUSED_eu_mb_wr = eu_mb_wr;
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wire [15:0] UNUSED_pc = pc;
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`endif
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`endif
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`ifdef DBG_HWBRK_1
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`ifdef DBG_HWBRK_1
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// Hardware Breakpoint/Watchpoint Register read select
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// Hardware Breakpoint/Watchpoint Register read select
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wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
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wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
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Line 816... |
.mem_bw (mem_bw) // Burst byte width
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.mem_bw (mem_bw) // Burst byte width
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);
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);
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`else
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`else
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assign dbg_uart_txd = 1'b1;
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assign dbg_uart_txd = 1'b1;
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wire UNUSED_dbg_uart_rxd = dbg_uart_rxd;
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`ifdef DBG_I2C
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`ifdef DBG_I2C
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`else
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`else
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assign dbg_addr = 6'h00;
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assign dbg_addr = 6'h00;
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assign dbg_din = 16'h0000;
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assign dbg_din = 16'h0000;
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assign dbg_rd = 1'b0;
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assign dbg_rd = 1'b0;
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Line 849... |
.dbg_dout (dbg_dout), // Debug register data output
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.dbg_dout (dbg_dout), // Debug register data output
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
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.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_rst (dbg_rst), // Debug unit reset
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.mem_burst (mem_burst), // Burst on going
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.mem_burst (mem_burst), // Burst on going
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.mem_burst_end (mem_burst_end), // End TX/RX burst
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.mem_burst_end (mem_burst_end), // End TX/RX burst
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.mem_burst_rd (mem_burst_rd), // Start TX burst
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.mem_burst_rd (mem_burst_rd), // Start TX burst
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.mem_burst_wr (mem_burst_wr), // Start RX burst
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.mem_burst_wr (mem_burst_wr), // Start RX burst
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.mem_bw (mem_bw) // Burst byte width
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.mem_bw (mem_bw) // Burst byte width
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);
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);
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`else
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`else
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assign dbg_i2c_sda_out = 1'b1;
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assign dbg_i2c_sda_out = 1'b1;
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wire [6:0] UNUSED_dbg_i2c_addr = dbg_i2c_addr;
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wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
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wire UNUSED_dbg_i2c_scl = dbg_i2c_scl;
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wire UNUSED_dbg_i2c_sda_in = dbg_i2c_sda_in;
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wire UNUSED_dbg_rd_rdy = dbg_rd_rdy;
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`endif
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`endif
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endmodule // omsp_dbg
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endmodule // omsp_dbg
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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