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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 74 $
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// $Rev: 84 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
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// $LastChangedDate: 2011-01-23 21:00:36 +0100 (Sun, 23 Jan 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module omsp_dbg (
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module omsp_dbg (
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parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
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parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
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parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
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parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
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parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
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parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
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`endif
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`endif
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// PUC is localy used as a data.
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reg [1:0] puc_sync;
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always @ (posedge mclk or posedge por)
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if (por) puc_sync <= 2'b11;
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else puc_sync <= {puc_sync[0] , puc};
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wire puc_s = puc_sync[1];
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
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// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
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//------------------------------------------------------------------------------------
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//------------------------------------------------------------------------------------
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reg [3:2] cpu_stat;
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reg [3:2] cpu_stat;
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wire cpu_stat_wr = reg_wr[CPU_STAT];
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wire cpu_stat_wr = reg_wr[CPU_STAT];
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wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
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wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
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wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
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wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) cpu_stat <= 2'b00;
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if (por) cpu_stat <= 2'b00;
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else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
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else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
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wire dbg_reset = cpu_ctl[`CPU_RST];
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wire dbg_reset = cpu_ctl[`CPU_RST];
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// Break after reset
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// Break after reset
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//--------------------------
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//--------------------------
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wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
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wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
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// Freeze peripherals
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// Freeze peripherals
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//--------------------------
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//--------------------------
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wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
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wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
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