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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_mem_backbone.v] - Diff between revs 202 and 205

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Rev 202 Rev 205
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 202 $
// $Rev: 205 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
// $LastChangedDate: 2015-07-15 22:59:52 +0200 (Wed, 15 Jul 2015) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 321... Line 321...
 
 
wire fe_pmem_save    = (~fe_pmem_en &  fe_pmem_en_dly) & ~cpu_halt_st;
wire fe_pmem_save    = (~fe_pmem_en &  fe_pmem_en_dly) & ~cpu_halt_st;
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) |  cpu_halt_st;
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) |  cpu_halt_st;
 
 
`ifdef CLOCK_GATING
`ifdef CLOCK_GATING
wire mclk_bckup;
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
                                  .clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
                                  .clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
 
`define MCLK_BCKUP           mclk_bckup_gated
`else
`else
wire UNUSED_scan_enable = scan_enable;
wire UNUSED_scan_enable = scan_enable;
wire mclk_bckup         = mclk;
`define MCLK_BCKUP           mclk        // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
`endif
 
 
reg  [15:0] pmem_dout_bckup;
reg  [15:0] pmem_dout_bckup;
always @(posedge mclk_bckup or posedge puc_rst)
always @(posedge `MCLK_BCKUP or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup     <=  16'h0000;
  if (puc_rst)              pmem_dout_bckup     <=  16'h0000;
`ifdef CLOCK_GATING
`ifdef CLOCK_GATING
  else                      pmem_dout_bckup     <=  pmem_dout;
  else                      pmem_dout_bckup     <=  pmem_dout;
`else
`else
  else if (fe_pmem_save)    pmem_dout_bckup     <=  pmem_dout;
  else if (fe_pmem_save)    pmem_dout_bckup     <=  pmem_dout;

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