OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430.v] - Diff between revs 53 and 67

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 53 Rev 67
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 53 $
// $Rev: 67 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-01-27 19:17:14 +0100 (Wed, 27 Jan 2010) $
// $LastChangedDate: 2010-03-07 12:59:38 +0100 (Sun, 07 Mar 2010) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
module  openMSP430 (
module  openMSP430 (
Line 146... Line 146...
wire          [1:0] dbg_mem_wr;
wire          [1:0] dbg_mem_wr;
 
 
wire         [15:0] per_dout_or;
wire         [15:0] per_dout_or;
wire         [15:0] per_dout_sfr;
wire         [15:0] per_dout_sfr;
wire         [15:0] per_dout_wdog;
wire         [15:0] per_dout_wdog;
 
wire         [15:0] per_dout_mpy;
wire         [15:0] per_dout_clk;
wire         [15:0] per_dout_clk;
 
 
 
 
//=============================================================================
//=============================================================================
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
Line 373... Line 374...
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
);
);
 
 
 
 
//=============================================================================
//=============================================================================
// 8)  PERIPHERALS' OUTPUT BUS
// 8)  HARDWARE MULTIPLIER
 
//=============================================================================
 
`ifdef MULTIPLIER
 
omsp_multiplier multiplier_0 (
 
 
 
// OUTPUTs
 
    .per_dout     (per_dout_mpy),  // Peripheral data output
 
 
 
// INPUTs
 
    .mclk         (mclk),          // Main system clock
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_wen      (per_wen),       // Peripheral write enable (high active)
 
    .puc          (puc)            // Main system reset
 
);
 
`else
 
assign per_dout_mpy = 16'h0000;
 
`endif
 
 
 
//=============================================================================
 
// 9)  PERIPHERALS' OUTPUT BUS
//=============================================================================
//=============================================================================
 
 
assign  per_dout_or  =  per_dout      |
assign  per_dout_or  =  per_dout      |
                        per_dout_clk  |
                        per_dout_clk  |
                        per_dout_sfr  |
                        per_dout_sfr  |
                        per_dout_wdog;
                        per_dout_wdog |
 
                        per_dout_mpy;
 
 
 
 
//=============================================================================
//=============================================================================
// 9)  DEBUG INTERFACE
// 10)  DEBUG INTERFACE
//=============================================================================
//=============================================================================
 
 
`ifdef DBG_EN
`ifdef DBG_EN
omsp_dbg dbg_0 (
omsp_dbg dbg_0 (
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.