| Line 25... |
Line 25... |
#
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#
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# File Name: rtlsim.sh
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# File Name: rtlsim.sh
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#
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#
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# Author(s):
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# Author(s):
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# - Olivier Girard, olgirard@gmail.com
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# - Olivier Girard, olgirard@gmail.com
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# - Mihai M., mmihai@delajii.net
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#
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#
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# $Rev: 73 $
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# $Rev: 94 $
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# $LastChangedBy: olivier.girard $
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# $LastChangedBy: olivier.girard $
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# $LastChangedDate: 2010-08-03 21:26:39 +0200 (Tue, 03 Aug 2010) $
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# $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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###############################################################################
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###############################################################################
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# Parameter Check #
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# Parameter Check #
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###############################################################################
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###############################################################################
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EXPECTED_ARGS=3
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EXPECTED_ARGS=3
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if [ $# -ne $EXPECTED_ARGS ]; then
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if [ $# -ne $EXPECTED_ARGS ]; then
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echo "ERROR : wrong number of arguments"
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echo "ERROR : wrong number of arguments"
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echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
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echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
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echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
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echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
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echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog"
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exit 1
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exit 1
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fi
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fi
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###############################################################################
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###############################################################################
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Line 68... |
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###############################################################################
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###############################################################################
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# Start verilog simulation #
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# Start verilog simulation #
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###############################################################################
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###############################################################################
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if [ "${MYVLOG:-iverilog}" = iverilog ]; then
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rm -rf simv
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rm -rf simv
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NODUMP=${OMSP_NODUMP-0}
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NODUMP=${OMSP_NODUMP-0}
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if [ $NODUMP -eq 1 ]
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if [ $NODUMP -eq 1 ]
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then
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then
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| Line 77... |
Line 81... |
else
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else
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iverilog -o simv -c $3
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iverilog -o simv -c $3
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fi
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fi
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./simv
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./simv
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else
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|
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NODUMP=${OMSP_NODUMP-0}
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if [ $NODUMP -eq 1 ] ; then
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vargs="+define+NODUMP"
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else
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vargs=""
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fi
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case $MYVLOG in
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cver* )
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vargs="$vargs +define+VXL" ;;
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verilog* )
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vargs="$vargs +define+VXL" ;;
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ncverilog* )
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vargs="$vargs +access+r" ;;
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vsim )
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# Modelsim
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if [ -d work ]; then vdel -all; fi
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vlib work
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exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all"
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esac
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echo "Running: $MYVLOG -f $3 $vargs"
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exec $MYVLOG -f $3 $vargs
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fi
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No newline at end of file
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No newline at end of file
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