URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.v] - Diff between revs 180 and 202

Rev 180	Rev 202
Line 535...	Line 535...

`ifdef ASIC_CLOCKING	`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER	`ifdef ACLK_DIVIDER
`bcsctl1_mask = bcsctl1_mask \| 16'h0030;`	`bcsctl1_mask = bcsctl1_mask \| 16'h0030;`
`endif	`endif
	`ifdef DMA_IF_EN
	`ifdef CPUOFF_EN
	`bcsctl1_mask = bcsctl1_mask \| 16'h0001;`
	`endif
	`ifdef OSCOFF_EN
	`bcsctl1_mask = bcsctl1_mask \| 16'h0002;`
	`endif
	`ifdef SCG0_EN
	`bcsctl1_mask = bcsctl1_mask \| 16'h0004;`
	`endif
	`ifdef SCG1_EN
	`bcsctl1_mask = bcsctl1_mask \| 16'h0008;`
	`endif
	`endif
`else	`else
`bcsctl1_mask = bcsctl1_mask \| 16'h0030;`	`bcsctl1_mask = bcsctl1_mask \| 16'h0030;`
`endif	`endif

`ifdef MCLK_MUX	`ifdef MCLK_MUX
Line 575...	Line 589...
`if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");`	`if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");`
`if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");`	`if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");`


`else	`else
`$display(" ===============================================");`	`tb_skip_finish("\| (this test is not supported in FPGA mode) \|");`
`$display("\| SIMULATION SKIPPED \|");`
`$display("\| (this test is not supported in FPGA mode) \|");`
`$display(" ===============================================");`
`$finish;`
`endif	`endif

`stimulus_done = 1;`	`stimulus_done = 1;`
`end`	`end`


`No newline at end of file`	`No newline at end of file`