URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_sync.v] - Diff between revs 200 and 202

Rev 200	Rev 202
Line 146...	Line 146...
`repeat(10) @(posedge mclk);`	`repeat(10) @(posedge mclk);`

`stimulus_done = 1;`	`stimulus_done = 1;`
`else	`else

`$display(" ===============================================");`	`tb_skip_finish("\| (serial debug interface I2C not included) \|");`
`$display("\| SIMULATION SKIPPED \|");`
`$display("\| (serial debug interface I2C not included) \|");`
`$display(" ===============================================");`
`$finish;`
`endif	`endif
`else	`else
	`tb_skip_finish("\| (serial debug interface not included) \|");`
`$display(" ===============================================");`
`$display("\| SIMULATION SKIPPED \|");`
`$display("\| (serial debug interface not included) \|");`
`$display(" ===============================================");`
`$finish;`
`endif	`endif
`end`	`end`

`task force_end_of_sim;`	`task force_end_of_sim;`
`begin`	`begin`
`repeat(10) @(posedge mclk);`	`repeat(10) @(posedge mclk);`
`$display(" ===============================================");`	`$display(" ===============================================");`
`$display("\| SIMULATION FAILED \|");`	`$display("\| SIMULATION FAILED \|");`
`$display("\| (some verilog stimulus checks failed) \|");`	`$display("\| (some verilog stimulus checks failed) \|");`
`$display(" ===============================================");`	`$display(" ===============================================");`
	`$display("");`
	`tb_extra_report;`
`$finish;`	`$finish;`
`end`	`end`
`endtask`	`endtask`

`No newline at end of file`	`No newline at end of file`