/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* DEBUG INTERFACE: UART */
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/* DEBUG INTERFACE: UART */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the UART debug interface: */
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/* Test the UART debug interface: */
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/* - Check RD/WR access to debugg registers. */
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/* - Check RD/WR access to debugg registers. */
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/* - Check RD Bursts. */
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/* - Check RD Bursts. */
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/* - Check WR Bursts. */
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/* - Check WR Bursts. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 106 $ */
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/* $Rev: 111 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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reg [15:0] dbg_id_pmem;
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reg [2:0] cpu_version;
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reg [15:0] dbg_id_dmem;
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reg cpu_asic;
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reg [4:0] user_version;
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reg [6:0] per_space;
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reg mpy_info;
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reg [8:0] dmem_size;
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reg [5:0] pmem_size;
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reg [31:0] dbg_id;
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reg [31:0] dbg_id;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_UART
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#1 dbg_en = 1;
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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// SEND UART SYNCHRONIZATION FRAME
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_tx(DBG_SYNC);
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dbg_uart_tx(DBG_SYNC);
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`ifdef DBG_RST_BRK_EN
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`ifdef DBG_RST_BRK_EN
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dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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`endif
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`endif
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// TEST CPU REGISTERS
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// TEST CPU REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_id_pmem = `PMEM_SIZE;
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dbg_id_dmem = `DMEM_SIZE;
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cpu_version = `CPU_VERSION;
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dbg_id = {dbg_id_pmem, dbg_id_dmem};
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`ifdef ASIC
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cpu_asic = 1'b1;
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`else
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cpu_asic = 1'b0;
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`endif
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user_version = `USER_VERSION;
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per_space = (`PER_SIZE >> 9);
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`ifdef MULTIPLIER
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mpy_info = 1'b1;
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`else
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mpy_info = 1'b0;
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`endif
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dmem_size = (`DMEM_SIZE >> 7);
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pmem_size = (`PMEM_SIZE >> 10);
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dbg_id = {pmem_size,
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dmem_size,
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mpy_info,
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per_space,
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user_version,
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cpu_asic,
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cpu_version};
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dbg_uart_wr(CPU_ID_LO , 16'hffff);
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dbg_uart_wr(CPU_ID_LO , 16'hffff);
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dbg_uart_rd(CPU_ID_LO);
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dbg_uart_rd(CPU_ID_LO);
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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dbg_uart_wr(CPU_ID_LO , 16'h0000);
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dbg_uart_wr(CPU_ID_LO , 16'h0000);
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dbg_uart_rd(CPU_ID_LO);
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dbg_uart_rd(CPU_ID_LO);
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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dbg_uart_wr(CPU_ID_HI , 16'hffff);
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dbg_uart_wr(CPU_ID_HI , 16'hffff);
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dbg_uart_rd(CPU_ID_HI);
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dbg_uart_rd(CPU_ID_HI);
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if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
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if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
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dbg_uart_wr(CPU_ID_HI , 16'h0000);
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dbg_uart_wr(CPU_ID_HI , 16'h0000);
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dbg_uart_rd(CPU_ID_HI);
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dbg_uart_rd(CPU_ID_HI);
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if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
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if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
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dbg_uart_wr(CPU_STAT , 16'hffff);
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dbg_uart_wr(CPU_STAT , 16'hffff);
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dbg_uart_rd(CPU_STAT);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect =====");
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dbg_uart_wr(CPU_STAT , 16'h0000);
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dbg_uart_wr(CPU_STAT , 16'h0000);
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dbg_uart_rd(CPU_STAT);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect =====");
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dbg_uart_wr(CPU_CTL , 16'hffff);
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dbg_uart_wr(CPU_CTL , 16'hffff);
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dbg_uart_rd(CPU_CTL);
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dbg_uart_rd(CPU_CTL);
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if (dbg_uart_buf !== 16'h0078) tb_error("====== CPU_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h0078) tb_error("====== CPU_CTL uncorrect =====");
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dbg_uart_wr(CPU_CTL , 16'h0000);
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dbg_uart_wr(CPU_CTL , 16'h0000);
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dbg_uart_rd(CPU_CTL);
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dbg_uart_rd(CPU_CTL);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL uncorrect =====");
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// TEST MEMORY CONTROL REGISTERS
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// TEST MEMORY CONTROL REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_uart_wr(MEM_CTL , 16'hfffe);
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dbg_uart_wr(MEM_CTL , 16'hfffe);
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dbg_uart_rd(MEM_CTL);
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dbg_uart_rd(MEM_CTL);
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if (dbg_uart_buf !== 16'h000E) tb_error("====== MEM_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h000E) tb_error("====== MEM_CTL uncorrect =====");
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dbg_uart_wr(MEM_CTL , 16'h0000);
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dbg_uart_wr(MEM_CTL , 16'h0000);
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dbg_uart_rd(MEM_CTL);
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dbg_uart_rd(MEM_CTL);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_CTL uncorrect =====");
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dbg_uart_wr(MEM_ADDR , 16'hffff);
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dbg_uart_wr(MEM_ADDR , 16'hffff);
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dbg_uart_rd(MEM_ADDR);
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dbg_uart_rd(MEM_ADDR);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== MEM_ADDR uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== MEM_ADDR uncorrect =====");
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dbg_uart_wr(MEM_ADDR , 16'h0000);
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dbg_uart_wr(MEM_ADDR , 16'h0000);
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dbg_uart_rd(MEM_ADDR);
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dbg_uart_rd(MEM_ADDR);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_ADDR uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_ADDR uncorrect =====");
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dbg_uart_wr(MEM_DATA , 16'hffff);
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dbg_uart_wr(MEM_DATA , 16'hffff);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== MEM_DATA uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== MEM_DATA uncorrect =====");
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dbg_uart_wr(MEM_DATA , 16'h0000);
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dbg_uart_wr(MEM_DATA , 16'h0000);
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dbg_uart_rd(MEM_DATA);
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA uncorrect =====");
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dbg_uart_wr(MEM_CNT , 16'hffff);
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dbg_uart_wr(MEM_CNT , 16'hffff);
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dbg_uart_rd(MEM_CNT);
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dbg_uart_rd(MEM_CNT);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== MEM_CNT uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== MEM_CNT uncorrect =====");
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dbg_uart_wr(MEM_CNT , 16'h0000);
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dbg_uart_wr(MEM_CNT , 16'h0000);
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dbg_uart_rd(MEM_CNT);
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dbg_uart_rd(MEM_CNT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_CNT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_CNT uncorrect =====");
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// TEST HARDWARE BREAKPOINT 0 REGISTERS
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// TEST HARDWARE BREAKPOINT 0 REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_0
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dbg_uart_wr(BRK0_CTL , 16'hffff);
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dbg_uart_wr(BRK0_CTL , 16'hffff);
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dbg_uart_rd(BRK0_CTL);
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dbg_uart_rd(BRK0_CTL);
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if (`HWBRK_RANGE)
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if (`HWBRK_RANGE)
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begin
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begin
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
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end
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end
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else
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else
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begin
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begin
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if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK0_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK0_CTL uncorrect =====");
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end
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end
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dbg_uart_wr(BRK0_CTL , 16'h0000);
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dbg_uart_wr(BRK0_CTL , 16'h0000);
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dbg_uart_rd(BRK0_CTL);
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dbg_uart_rd(BRK0_CTL);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect =====");
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dbg_uart_wr(BRK0_STAT , 16'hffff);
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dbg_uart_wr(BRK0_STAT , 16'hffff);
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dbg_uart_rd(BRK0_STAT);
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dbg_uart_rd(BRK0_STAT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect =====");
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dbg_uart_wr(BRK0_STAT , 16'h0000);
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dbg_uart_wr(BRK0_STAT , 16'h0000);
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dbg_uart_rd(BRK0_STAT);
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dbg_uart_rd(BRK0_STAT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect =====");
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dbg_uart_wr(BRK0_ADDR0 , 16'hffff);
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dbg_uart_wr(BRK0_ADDR0 , 16'hffff);
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dbg_uart_rd(BRK0_ADDR0);
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dbg_uart_rd(BRK0_ADDR0);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK0_ADDR0 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK0_ADDR0 uncorrect =====");
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dbg_uart_wr(BRK0_ADDR0 , 16'h0000);
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dbg_uart_wr(BRK0_ADDR0 , 16'h0000);
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dbg_uart_rd(BRK0_ADDR0);
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dbg_uart_rd(BRK0_ADDR0);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_ADDR0 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_ADDR0 uncorrect =====");
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dbg_uart_wr(BRK0_ADDR1 , 16'hffff);
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dbg_uart_wr(BRK0_ADDR1 , 16'hffff);
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dbg_uart_rd(BRK0_ADDR1);
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dbg_uart_rd(BRK0_ADDR1);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK0_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK0_ADDR1 uncorrect =====");
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dbg_uart_wr(BRK0_ADDR1 , 16'h0000);
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dbg_uart_wr(BRK0_ADDR1 , 16'h0000);
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dbg_uart_rd(BRK0_ADDR1);
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dbg_uart_rd(BRK0_ADDR1);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_ADDR1 uncorrect =====");
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`endif
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// TEST HARDWARE BREAKPOINT 1 REGISTERS
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// TEST HARDWARE BREAKPOINT 1 REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_1
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dbg_uart_wr(BRK1_CTL , 16'hffff);
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dbg_uart_wr(BRK1_CTL , 16'hffff);
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dbg_uart_rd(BRK1_CTL);
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dbg_uart_rd(BRK1_CTL);
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if (`HWBRK_RANGE)
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if (`HWBRK_RANGE)
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begin
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begin
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
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end
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end
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else
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else
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begin
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begin
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if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK1_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK1_CTL uncorrect =====");
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end
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end
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dbg_uart_wr(BRK1_CTL , 16'h0000);
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dbg_uart_wr(BRK1_CTL , 16'h0000);
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dbg_uart_rd(BRK1_CTL);
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dbg_uart_rd(BRK1_CTL);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect =====");
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dbg_uart_wr(BRK1_STAT , 16'hffff);
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dbg_uart_wr(BRK1_STAT , 16'hffff);
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dbg_uart_rd(BRK1_STAT);
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect =====");
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dbg_uart_wr(BRK1_STAT , 16'h0000);
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dbg_uart_wr(BRK1_STAT , 16'h0000);
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dbg_uart_rd(BRK1_STAT);
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect =====");
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|
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dbg_uart_wr(BRK1_ADDR0 , 16'hffff);
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dbg_uart_wr(BRK1_ADDR0 , 16'hffff);
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dbg_uart_rd(BRK1_ADDR0);
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dbg_uart_rd(BRK1_ADDR0);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK1_ADDR0 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK1_ADDR0 uncorrect =====");
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dbg_uart_wr(BRK1_ADDR0 , 16'h0000);
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dbg_uart_wr(BRK1_ADDR0 , 16'h0000);
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dbg_uart_rd(BRK1_ADDR0);
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dbg_uart_rd(BRK1_ADDR0);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_ADDR0 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_ADDR0 uncorrect =====");
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dbg_uart_wr(BRK1_ADDR1 , 16'hffff);
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dbg_uart_wr(BRK1_ADDR1 , 16'hffff);
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dbg_uart_rd(BRK1_ADDR1);
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dbg_uart_rd(BRK1_ADDR1);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK1_ADDR1 uncorrect =====");
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK1_ADDR1 uncorrect =====");
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dbg_uart_wr(BRK1_ADDR1 , 16'h0000);
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dbg_uart_wr(BRK1_ADDR1 , 16'h0000);
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dbg_uart_rd(BRK1_ADDR1);
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dbg_uart_rd(BRK1_ADDR1);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_ADDR1 uncorrect =====");
|
|
`endif
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// TEST HARDWARE BREAKPOINT 2 REGISTERS
|
// TEST HARDWARE BREAKPOINT 2 REGISTERS
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
`ifdef DBG_HWBRK_2
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dbg_uart_wr(BRK2_CTL , 16'hffff);
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dbg_uart_wr(BRK2_CTL , 16'hffff);
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dbg_uart_rd(BRK2_CTL);
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dbg_uart_rd(BRK2_CTL);
|
if (`HWBRK_RANGE)
|
if (`HWBRK_RANGE)
|
begin
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begin
|
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
|
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK2_CTL uncorrect =====");
|
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK2_CTL uncorrect =====");
|
end
|
end
|
dbg_uart_wr(BRK2_CTL , 16'h0000);
|
dbg_uart_wr(BRK2_CTL , 16'h0000);
|
dbg_uart_rd(BRK2_CTL);
|
dbg_uart_rd(BRK2_CTL);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect =====");
|
|
|
dbg_uart_wr(BRK2_STAT , 16'hffff);
|
dbg_uart_wr(BRK2_STAT , 16'hffff);
|
dbg_uart_rd(BRK2_STAT);
|
dbg_uart_rd(BRK2_STAT);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect =====");
|
dbg_uart_wr(BRK2_STAT , 16'h0000);
|
dbg_uart_wr(BRK2_STAT , 16'h0000);
|
dbg_uart_rd(BRK2_STAT);
|
dbg_uart_rd(BRK2_STAT);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect =====");
|
|
|
dbg_uart_wr(BRK2_ADDR0 , 16'hffff);
|
dbg_uart_wr(BRK2_ADDR0 , 16'hffff);
|
dbg_uart_rd(BRK2_ADDR0);
|
dbg_uart_rd(BRK2_ADDR0);
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK2_ADDR0 uncorrect =====");
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK2_ADDR0 uncorrect =====");
|
dbg_uart_wr(BRK2_ADDR0 , 16'h0000);
|
dbg_uart_wr(BRK2_ADDR0 , 16'h0000);
|
dbg_uart_rd(BRK2_ADDR0);
|
dbg_uart_rd(BRK2_ADDR0);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_ADDR0 uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_ADDR0 uncorrect =====");
|
|
|
dbg_uart_wr(BRK2_ADDR1 , 16'hffff);
|
dbg_uart_wr(BRK2_ADDR1 , 16'hffff);
|
dbg_uart_rd(BRK2_ADDR1);
|
dbg_uart_rd(BRK2_ADDR1);
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK2_ADDR1 uncorrect =====");
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK2_ADDR1 uncorrect =====");
|
dbg_uart_wr(BRK2_ADDR1 , 16'h0000);
|
dbg_uart_wr(BRK2_ADDR1 , 16'h0000);
|
dbg_uart_rd(BRK2_ADDR1);
|
dbg_uart_rd(BRK2_ADDR1);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_ADDR1 uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_ADDR1 uncorrect =====");
|
|
`endif
|
|
|
// TEST HARDWARE BREAKPOINT 3 REGISTERS
|
// TEST HARDWARE BREAKPOINT 3 REGISTERS
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
`ifdef DBG_HWBRK_3
|
dbg_uart_wr(BRK3_CTL , 16'hffff);
|
dbg_uart_wr(BRK3_CTL , 16'hffff);
|
dbg_uart_rd(BRK3_CTL);
|
dbg_uart_rd(BRK3_CTL);
|
if (`HWBRK_RANGE)
|
if (`HWBRK_RANGE)
|
begin
|
begin
|
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
|
if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK3_CTL uncorrect =====");
|
if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK3_CTL uncorrect =====");
|
end
|
end
|
dbg_uart_wr(BRK3_CTL , 16'h0000);
|
dbg_uart_wr(BRK3_CTL , 16'h0000);
|
dbg_uart_rd(BRK3_CTL);
|
dbg_uart_rd(BRK3_CTL);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect =====");
|
|
|
dbg_uart_wr(BRK3_STAT , 16'hffff);
|
dbg_uart_wr(BRK3_STAT , 16'hffff);
|
dbg_uart_rd(BRK3_STAT);
|
dbg_uart_rd(BRK3_STAT);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect =====");
|
dbg_uart_wr(BRK3_STAT , 16'h0000);
|
dbg_uart_wr(BRK3_STAT , 16'h0000);
|
dbg_uart_rd(BRK3_STAT);
|
dbg_uart_rd(BRK3_STAT);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect =====");
|
|
|
dbg_uart_wr(BRK3_ADDR0 , 16'hffff);
|
dbg_uart_wr(BRK3_ADDR0 , 16'hffff);
|
dbg_uart_rd(BRK3_ADDR0);
|
dbg_uart_rd(BRK3_ADDR0);
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK3_ADDR0 uncorrect =====");
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK3_ADDR0 uncorrect =====");
|
dbg_uart_wr(BRK3_ADDR0 , 16'h0000);
|
dbg_uart_wr(BRK3_ADDR0 , 16'h0000);
|
dbg_uart_rd(BRK3_ADDR0);
|
dbg_uart_rd(BRK3_ADDR0);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_ADDR0 uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_ADDR0 uncorrect =====");
|
|
|
dbg_uart_wr(BRK3_ADDR1 , 16'hffff);
|
dbg_uart_wr(BRK3_ADDR1 , 16'hffff);
|
dbg_uart_rd(BRK3_ADDR1);
|
dbg_uart_rd(BRK3_ADDR1);
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK3_ADDR1 uncorrect =====");
|
if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK3_ADDR1 uncorrect =====");
|
dbg_uart_wr(BRK3_ADDR1 , 16'h0000);
|
dbg_uart_wr(BRK3_ADDR1 , 16'h0000);
|
dbg_uart_rd(BRK3_ADDR1);
|
dbg_uart_rd(BRK3_ADDR1);
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_ADDR1 uncorrect =====");
|
if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_ADDR1 uncorrect =====");
|
|
`endif
|
|
|
// TEST 16B WRITE BURSTS (MEMORY)
|
// TEST 16B WRITE BURSTS (MEMORY)
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
|
dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
|
|
dbg_uart_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
|
dbg_uart_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
|
dbg_uart_tx16(16'h1234); // write 1st data
|
dbg_uart_tx16(16'h1234); // write 1st data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem200 !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
|
if (mem200 !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
|
dbg_uart_tx16(16'h5678); // write 2nd data
|
dbg_uart_tx16(16'h5678); // write 2nd data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem202 !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
|
if (mem202 !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
|
dbg_uart_tx16(16'h9abc); // write 3rd data
|
dbg_uart_tx16(16'h9abc); // write 3rd data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem204 !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
|
if (mem204 !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
|
dbg_uart_tx16(16'hdef0); // write 4th data
|
dbg_uart_tx16(16'hdef0); // write 4th data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
|
if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
|
dbg_uart_tx16(16'h0fed); // write 5th data
|
dbg_uart_tx16(16'h0fed); // write 5th data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
|
if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
|
|
|
dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
|
dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
|
|
dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
|
dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
|
dbg_uart_rx16(); // read 1st data
|
dbg_uart_rx16(); // read 1st data
|
if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
|
if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
|
dbg_uart_rx16(); // read 2nd data
|
dbg_uart_rx16(); // read 2nd data
|
if (dbg_uart_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
|
if (dbg_uart_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
|
dbg_uart_rx16(); // read 3rd data
|
dbg_uart_rx16(); // read 3rd data
|
if (dbg_uart_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
|
if (dbg_uart_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
|
dbg_uart_rx16(); // read 4th data
|
dbg_uart_rx16(); // read 4th data
|
if (dbg_uart_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
|
if (dbg_uart_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
|
dbg_uart_rx16(); // read 5th data
|
dbg_uart_rx16(); // read 5th data
|
if (dbg_uart_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
|
if (dbg_uart_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
|
|
|
|
|
// TEST 16B WRITE BURSTS (CPU REGISTERS)
|
// TEST 16B WRITE BURSTS (CPU REGISTERS)
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
|
dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
|
|
dbg_uart_wr(MEM_CTL, 16'h0007); // Start burst to 16 bit cpu register write
|
dbg_uart_wr(MEM_CTL, 16'h0007); // Start burst to 16 bit cpu register write
|
dbg_uart_tx16(16'hcba9); // write 1st data
|
dbg_uart_tx16(16'hcba9); // write 1st data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (r5 !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
|
if (r5 !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
|
dbg_uart_tx16(16'h8765); // write 2nd data
|
dbg_uart_tx16(16'h8765); // write 2nd data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (r6 !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
|
if (r6 !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
|
dbg_uart_tx16(16'h4321); // write 3rd data
|
dbg_uart_tx16(16'h4321); // write 3rd data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (r7 !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
|
if (r7 !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
|
dbg_uart_tx16(16'h0123); // write 4th data
|
dbg_uart_tx16(16'h0123); // write 4th data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (r8 !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
|
if (r8 !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
|
dbg_uart_tx16(16'h4567); // write 5th data
|
dbg_uart_tx16(16'h4567); // write 5th data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (r9 !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
|
if (r9 !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
|
|
|
dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
|
dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
|
|
dbg_uart_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read
|
dbg_uart_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read
|
dbg_uart_rx16(); // read 1st data
|
dbg_uart_rx16(); // read 1st data
|
if (dbg_uart_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
|
if (dbg_uart_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
|
dbg_uart_rx16(); // read 2nd data
|
dbg_uart_rx16(); // read 2nd data
|
if (dbg_uart_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
|
if (dbg_uart_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
|
dbg_uart_rx16(); // read 3rd data
|
dbg_uart_rx16(); // read 3rd data
|
if (dbg_uart_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
|
if (dbg_uart_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
|
dbg_uart_rx16(); // read 4th data
|
dbg_uart_rx16(); // read 4th data
|
if (dbg_uart_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
|
if (dbg_uart_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
|
dbg_uart_rx16(); // read 5th data
|
dbg_uart_rx16(); // read 5th data
|
if (dbg_uart_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
|
if (dbg_uart_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
|
|
|
|
|
// TEST 8B WRITE BURSTS (MEMORY)
|
// TEST 8B WRITE BURSTS (MEMORY)
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
|
dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0210
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
|
|
dbg_uart_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
|
dbg_uart_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
|
dbg_uart_tx(8'h91); // write 1st data
|
dbg_uart_tx(8'h91); // write 1st data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem200 !== 16'h1291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
|
if (mem200 !== 16'h1291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
|
dbg_uart_tx(8'h82); // write 2nd data
|
dbg_uart_tx(8'h82); // write 2nd data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem200 !== 16'h8291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
|
if (mem200 !== 16'h8291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
|
dbg_uart_tx(8'h73); // write 3rd data
|
dbg_uart_tx(8'h73); // write 3rd data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem202 !== 16'h5673) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
|
if (mem202 !== 16'h5673) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
|
dbg_uart_tx(8'h64); // write 4th data
|
dbg_uart_tx(8'h64); // write 4th data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
|
if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
|
dbg_uart_tx(8'h55); // write 5th data
|
dbg_uart_tx(8'h55); // write 5th data
|
repeat(12) @(posedge mclk);
|
repeat(12) @(posedge mclk);
|
if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
|
if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
|
|
|
dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
|
dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
|
|
dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
|
dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
|
dbg_uart_rx8(); // read 1st data
|
dbg_uart_rx8(); // read 1st data
|
if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
|
if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
|
dbg_uart_rx8(); // read 2nd data
|
dbg_uart_rx8(); // read 2nd data
|
if (dbg_uart_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
|
if (dbg_uart_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
|
dbg_uart_rx8(); // read 3rd data
|
dbg_uart_rx8(); // read 3rd data
|
if (dbg_uart_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
|
if (dbg_uart_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
|
dbg_uart_rx8(); // read 4th data
|
dbg_uart_rx8(); // read 4th data
|
if (dbg_uart_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
|
if (dbg_uart_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
|
dbg_uart_rx8(); // read 5th data
|
dbg_uart_rx8(); // read 5th data
|
if (dbg_uart_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
|
if (dbg_uart_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
|
|
|
|
|
|
|
|
|
|
|
dbg_uart_wr(CPU_CTL , 16'h0002);
|
dbg_uart_wr(CPU_CTL , 16'h0002);
|
repeat(10) @(posedge mclk);
|
repeat(10) @(posedge mclk);
|
|
|
stimulus_done = 1;
|
stimulus_done = 1;
|
|
`else
|
|
|
|
$display(" ===============================================");
|
|
$display("| SIMULATION SKIPPED |");
|
|
$display("| (serial debug interface UART not included) |");
|
|
$display(" ===============================================");
|
|
$finish;
|
|
`endif
|
|
`else
|
|
|
|
$display(" ===============================================");
|
|
$display("| SIMULATION SKIPPED |");
|
|
$display("| (serial debug interface not included) |");
|
|
$display(" ===============================================");
|
|
$finish;
|
|
`endif
|
end
|
end
|
|
|
|
|
