| Line 30... |
Line 30... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $Rev: 33 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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reg [3:0] dbg_id_rom;
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reg [3:0] dbg_id_pmem;
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reg [3:0] dbg_id_ram;
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reg [3:0] dbg_id_dmem;
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reg [31:0] dbg_id;
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reg [31:0] dbg_id;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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| Line 54... |
Line 54... |
// SEND UART SYNCHRONIZATION FRAME
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_tx(DBG_SYNC);
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dbg_uart_tx(DBG_SYNC);
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// TEST CPU REGISTERS
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// TEST CPU REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_id_rom = `ROM_AWIDTH;
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dbg_id_pmem = `PMEM_AWIDTH;
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dbg_id_ram = `RAM_AWIDTH;
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dbg_id_dmem = `DMEM_AWIDTH;
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dbg_id = {`DBG_ID, dbg_id_rom, dbg_id_ram};
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dbg_id = {`DBG_ID, dbg_id_pmem, dbg_id_dmem};
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dbg_uart_wr(CPU_ID_LO , 16'hffff);
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dbg_uart_wr(CPU_ID_LO , 16'hffff);
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dbg_uart_rd(CPU_ID_LO);
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dbg_uart_rd(CPU_ID_LO);
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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dbg_uart_wr(CPU_ID_LO , 16'h0000);
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dbg_uart_wr(CPU_ID_LO , 16'h0000);
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