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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* DEBUG INTERFACE */
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/*---------------------------------------------------------------------------*/
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/* Test the debug interface: */
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/* - Check Hardware breakpoint unit 1. */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 154 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $ */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_UART
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`ifdef DBG_HWBRK_1
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_tx(DBG_SYNC);
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`ifdef DBG_RST_BRK_EN
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dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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`endif
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// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
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//----------------------------------------------------------------------
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// RESET & BREAK
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dbg_uart_wr(CPU_CTL, 16'h0060);
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dbg_uart_wr(CPU_CTL, 16'h0020);
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// CONFIGURE BREAKPOINT (DISABLED) & RUN
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dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04));
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dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18));
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dbg_uart_wr(BRK1_CTL, 16'h000C);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// RESET & BREAK
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dbg_uart_wr(CPU_CTL, 16'h0060);
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dbg_uart_wr(CPU_CTL, 16'h0020);
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dbg_uart_wr(CPU_STAT, 16'h00ff);
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// CHECK
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if (mem200 === 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 =====");
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// CONFIGURE BREAKPOINT (ENABLED) & RUN
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dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04));
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dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18));
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dbg_uart_wr(BRK1_CTL, 16'h000D);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h04)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 =====");
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if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0001);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 =====");
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// RE-RUN
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dbg_uart_wr(BRK1_ADDR0, 16'h0000);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// RE-CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 =====");
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if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0004);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 =====");
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// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
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//----------------------------------------------------------------------
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if (`HWBRK_RANGE)
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begin
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// RESET, BREAK & CLEAR STATUS
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dbg_uart_wr(CPU_CTL, 16'h0060);
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dbg_uart_wr(CPU_CTL, 16'h0020);
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dbg_uart_wr(BRK1_STAT, 16'h00ff);
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dbg_uart_wr(CPU_STAT, 16'h00ff);
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// CONFIGURE BREAKPOINT(ENABLED) & RUN
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dbg_uart_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE-'h100));
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dbg_uart_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h20));
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dbg_uart_wr(BRK1_CTL, 16'h001D);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// CHECK
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if (r0 !== ('h10000-`PMEM_SIZE)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 =====");
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if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0010);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
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end
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// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
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//----------------------------------------------------------------------------
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// RESET, BREAK & CLEAR STATUS
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dbg_uart_wr(CPU_CTL, 16'h0060);
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dbg_uart_wr(CPU_CTL, 16'h0020);
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dbg_uart_wr(BRK1_STAT, 16'h00ff);
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dbg_uart_wr(CPU_STAT, 16'h00ff);
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// CONFIGURE BREAKPOINT (ENABLED) & RUN
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dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004));
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dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008));
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dbg_uart_wr(BRK1_CTL, 16'h0005);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
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if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0001);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 =====");
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// RE-RUN
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// RE-CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
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if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0004);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 =====");
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// RE-RUN
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
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if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0001);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 =====");
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// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
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//-----------------------------------------------------------------------------
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// RESET, BREAK & CLEAR STATUS
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dbg_uart_wr(CPU_CTL, 16'h0060);
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dbg_uart_wr(CPU_CTL, 16'h0020);
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dbg_uart_wr(BRK1_STAT, 16'h00ff);
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dbg_uart_wr(CPU_STAT, 16'h00ff);
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// CONFIGURE BREAKPOINT (ENABLED) & RUN
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dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004));
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dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008));
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dbg_uart_wr(BRK1_CTL, 16'h0006);
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
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if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0002);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
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// RE-RUN
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// RE-CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
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if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0008);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
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// RE-RUN
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// RE-CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
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if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0002);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
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// RE-RUN
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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// RE-CHECK
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if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
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if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
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dbg_uart_rd(BRK1_STAT);
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if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
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dbg_uart_wr(BRK1_STAT, 16'h0008);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
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|
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// RE-RUN
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(100) @(posedge mclk);
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|
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// RE-CHECK
|
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if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
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if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
|
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dbg_uart_rd(BRK1_STAT);
|
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if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
|
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dbg_uart_wr(BRK1_STAT, 16'h0002);
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dbg_uart_rd(CPU_STAT);
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if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
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|
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|
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// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE
|
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//----------------------------------------------------------------------------------
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// RESET, BREAK & CLEAR STATUS
|
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dbg_uart_wr(CPU_CTL, 16'h0060);
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dbg_uart_wr(CPU_CTL, 16'h0020);
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dbg_uart_wr(BRK1_STAT, 16'h00ff);
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dbg_uart_wr(CPU_STAT, 16'h00ff);
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// CONFIGURE BREAKPOINT (ENABLED) & RUN
|
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dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004));
|
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dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008));
|
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dbg_uart_wr(BRK1_CTL, 16'h0007);
|
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dbg_uart_wr(CPU_CTL, 16'h0002);
|
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repeat(100) @(posedge mclk);
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|
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// CHECK
|
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if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 =====");
|
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dbg_uart_rd(CPU_STAT);
|
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if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 =====");
|
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dbg_uart_rd(BRK1_STAT);
|
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if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 =====");
|
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dbg_uart_wr(BRK1_STAT, 16'h0002);
|
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dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
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|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h44)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0008);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0002);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0008);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0001);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0004);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 =====");
|
|
|
|
|
|
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
|
|
//----------------------------------------------------------------------------
|
|
if (`HWBRK_RANGE)
|
|
begin
|
|
|
|
// RESET, BREAK & CLEAR STATUS
|
|
dbg_uart_wr(CPU_CTL, 16'h0060);
|
|
dbg_uart_wr(CPU_CTL, 16'h0020);
|
|
dbg_uart_wr(BRK1_STAT, 16'h00ff);
|
|
dbg_uart_wr(CPU_STAT, 16'h00ff);
|
|
|
|
|
|
// CONFIGURE BREAKPOINT (ENABLED) & RUN
|
|
dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001));
|
|
dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005));
|
|
dbg_uart_wr(BRK1_CTL, 16'h0015);
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0010);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
|
|
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0010);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
|
|
end
|
|
|
|
|
|
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
|
|
//-----------------------------------------------------------------------------
|
|
if (`HWBRK_RANGE)
|
|
begin
|
|
|
|
// RESET, BREAK & CLEAR STATUS
|
|
dbg_uart_wr(CPU_CTL, 16'h0060);
|
|
dbg_uart_wr(CPU_CTL, 16'h0020);
|
|
dbg_uart_wr(BRK1_STAT, 16'h00ff);
|
|
dbg_uart_wr(CPU_STAT, 16'h00ff);
|
|
|
|
|
|
// CONFIGURE BREAKPOINT (ENABLED) & RUN
|
|
dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001));
|
|
dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005));
|
|
dbg_uart_wr(BRK1_CTL, 16'h0016);
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
|
|
end
|
|
|
|
// HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
|
|
//----------------------------------------------------------------------------------
|
|
if (`HWBRK_RANGE)
|
|
begin
|
|
|
|
// RESET, BREAK & CLEAR STATUS
|
|
dbg_uart_wr(CPU_CTL, 16'h0060);
|
|
dbg_uart_wr(CPU_CTL, 16'h0020);
|
|
dbg_uart_wr(BRK1_STAT, 16'h00ff);
|
|
dbg_uart_wr(CPU_STAT, 16'h00ff);
|
|
|
|
|
|
// CONFIGURE BREAKPOINT (ENABLED) & RUN
|
|
dbg_uart_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001));
|
|
dbg_uart_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005));
|
|
dbg_uart_wr(BRK1_CTL, 16'h0017);
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h36)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h3a)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 =====");
|
|
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0010);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 =====");
|
|
|
|
// RE-RUN
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
// RE-CHECK
|
|
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 =====");
|
|
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 =====");
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
|
|
dbg_uart_rd(BRK1_STAT);
|
|
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
|
|
dbg_uart_wr(BRK1_STAT, 16'h0020);
|
|
dbg_uart_rd(CPU_STAT);
|
|
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
|
|
|
|
end
|
|
|
|
// RE-RUN UNTIL END OF PATTERN
|
|
dbg_uart_wr(BRK1_CTL, 16'h0000);
|
|
dbg_uart_wr(CPU_CTL, 16'h0002);
|
|
repeat(100) @(posedge mclk);
|
|
|
|
|
|
stimulus_done = 1;
|
|
`else
|
|
|
|
$display(" ===============================================");
|
|
$display("| SIMULATION SKIPPED |");
|
|
$display("| (hardware breakpoint unit 1 not included) |");
|
|
$display(" ===============================================");
|
|
$finish;
|
|
`endif
|
|
`else
|
|
|
|
$display(" ===============================================");
|
|
$display("| SIMULATION SKIPPED |");
|
|
$display("| (serial debug interface UART not included) |");
|
|
$display(" ===============================================");
|
|
$finish;
|
|
`endif
|
|
`else
|
|
|
|
$display(" ===============================================");
|
|
$display("| SIMULATION SKIPPED |");
|
|
$display("| (serial debug interface not included) |");
|
|
$display(" ===============================================");
|
|
$finish;
|
|
`endif
|
|
end
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
