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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* DEBUG INTERFACE */
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/*---------------------------------------------------------------------------*/
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/* Test the debug interface: */
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/* - CPU Control features. */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/*===========================================================================*/
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integer test_nr;
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integer test_var;
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integer dco_clk_counter;
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always @ (negedge dco_clk)
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dco_clk_counter <= dco_clk_counter+1;
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integer dbg_clk_counter;
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always @ (negedge dbg_clk)
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dbg_clk_counter <= dbg_clk_counter+1;
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initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_UART
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`ifdef ASIC
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test_nr = 0;
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#1 dbg_en = 0;
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repeat(30) @(posedge dco_clk);
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stimulus_done = 0;
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// Make sure the CPU always starts executing when the
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// debug interface is disabled during POR.
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// Also make sure that the debug interface clock is stopped
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// and that it is under reset
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//--------------------------------------------------------
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dbg_en = 0;
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test_nr = 1;
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@(negedge dco_clk) dbg_clk_counter = 0;
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repeat(300) @(posedge dco_clk);
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if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
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if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) =====");
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if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");
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test_var = r14;
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// Make sure that enabling the debug interface after the POR
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// don't stop the cpu
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// Also make sure that the debug interface clock is running
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// and that its reset is released
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//--------------------------------------------------------
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dbg_en = 1;
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test_nr = 2;
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@(negedge dco_clk) dbg_clk_counter = 0;
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repeat(300) @(posedge dco_clk);
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if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");
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if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) =====");
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if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");
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// Make sure that disabling the CPU with debug enabled
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// will stop the CPU
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// Also make sure that the debug interface clock is stopped
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// and that it is NOT under reset
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//--------------------------------------------------------
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cpu_en = 0;
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dbg_en = 1;
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test_nr = 3;
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#(6*50);
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test_var = r14;
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dbg_clk_counter = 0;
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#(300*50);
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if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) =====");
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if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) =====");
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if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");
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cpu_en = 1;
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repeat(6) @(negedge dco_clk);
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// Create POR with debug enable and observe the
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// behavior depending on the DBG_RST_BRK_EN define
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//--------------------------------------------------------
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dbg_en = 1;
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test_nr = 4;
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@(posedge dco_clk); // Generate POR
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reset_n = 1'b0;
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@(posedge dco_clk);
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reset_n = 1'b1;
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repeat(300) @(posedge dco_clk);
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`ifdef DBG_RST_BRK_EN
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if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
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`else
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if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
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`endif
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// Send uart synchronization frame
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dbg_uart_tx(DBG_SYNC);
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// Check CPU_CTL reset value
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dbg_uart_rd(CPU_CTL);
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`ifdef DBG_RST_BRK_EN
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if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
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`else
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if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
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`endif
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// Make sure that DBG_EN resets the debug interface
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//--------------------------------------------------------
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test_nr = 5;
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// Let the CPU run
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(300) @(posedge dco_clk);
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dbg_uart_wr(CPU_CTL, 16'h0000);
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dbg_uart_wr(MEM_DATA, 16'haa55);
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dbg_uart_rd(CPU_CTL);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");
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test_var = r14; // Backup the current register value
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@(posedge dco_clk); // Resets the debug interface
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dbg_en = 1'b0;
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repeat(2) @(posedge dco_clk);
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dbg_en = 1'b1;
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// Make sure that the register was not reseted
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if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");
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repeat(2) @(posedge dco_clk);
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// Send uart synchronization frame
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dbg_uart_tx(DBG_SYNC);
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// Check CPU_CTL reset value
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dbg_uart_rd(CPU_CTL);
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`ifdef DBG_RST_BRK_EN
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if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
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`else
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if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
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`endif
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
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// Make sure that RESET_N resets the debug interface
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//--------------------------------------------------------
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test_nr = 6;
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// Let the CPU run
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dbg_uart_wr(CPU_CTL, 16'h0002);
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repeat(300) @(posedge dco_clk);
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dbg_uart_wr(CPU_CTL, 16'h0000);
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dbg_uart_wr(MEM_DATA, 16'haa55);
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dbg_uart_rd(CPU_CTL);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");
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test_nr = 7;
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@(posedge dco_clk); // Generates POR
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reset_n = 1'b0;
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repeat(2) @(posedge dco_clk);
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reset_n = 1'b1;
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// Make sure that the register was reseted
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if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");
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repeat(2) @(posedge dco_clk);
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// Send uart synchronization frame
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dbg_uart_tx(DBG_SYNC);
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test_nr = 8;
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// Check CPU_CTL reset value
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dbg_uart_rd(CPU_CTL);
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`ifdef DBG_RST_BRK_EN
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if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
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`else
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if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
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`endif
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dbg_uart_rd(MEM_DATA);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
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// Let the CPU run
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dbg_uart_wr(CPU_CTL, 16'h0002);
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test_nr = 9;
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// Generate IRQ to terminate the test pattern
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irq[1] = 1'b1;
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@(r13);
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irq[1] = 1'b0;
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stimulus_done = 1;
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in FPGA mode) |");
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$display(" ===============================================");
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$finish;
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`endif
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface UART not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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end
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