| Line 19... |
Line 19... |
/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* SANDBOX */
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/* COREMARK */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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| Line 53... |
Line 53... |
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//---------------------------------------
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//---------------------------------------
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// Check CPU configuration
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// Check CPU configuration
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//---------------------------------------
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//---------------------------------------
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|
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if ((`PMEM_SIZE !== 24576) || (`DMEM_SIZE !== 16384))
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if ((`PMEM_SIZE !== 55296) || (`DMEM_SIZE !== 5120))
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION ERROR |");
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$display("| SIMULATION ERROR |");
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$display("| |");
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$display("| |");
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$display("| Core must be configured for: |");
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$display("| Core must be configured for: |");
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$display("| - 24kB program memory |");
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$display("| - 54kB program memory |");
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$display("| - 16kB data memory |");
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$display("| - 5kB data memory |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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end
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end
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|
|
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// Disable watchdog
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// (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
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`ifdef WATCHDOG
|
|
force dut.watchdog_0.wdtcnt = 16'h0000;
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`endif
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|
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//---------------------------------------
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//---------------------------------------
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// Number of benchmark iteration
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// Number of benchmark iteration
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// (Must match the C-code value)
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// (Must match the C-code value)
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//---------------------------------------
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//---------------------------------------
|
|
|
| Line 88... |
Line 94... |
mclk_period = mclk_end_time-mclk_start_time;
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mclk_period = mclk_end_time-mclk_start_time;
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mclk_frequency = 1000/mclk_period;
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mclk_frequency = 1000/mclk_period;
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$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz", mclk_frequency);
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$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz", mclk_frequency);
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|
|
//---------------------------------------
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//---------------------------------------
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// Measure Dhrystone run time
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// Measure CoreMark run time
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//---------------------------------------
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//---------------------------------------
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|
|
// Detect beginning of run
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// Detect beginning of run
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@(posedge p2_dout[1]);
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@(posedge p2_dout[1]);
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coremark_start_time = $time;
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coremark_start_time = $time;
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$timeformat(-3, 3, " ms", 10);
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$timeformat(-3, 3, " ms", 10);
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$display("INFO-VERILOG: CoreMark loop started at %t ", coremark_start_time);
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$display("INFO-VERILOG: CoreMark loop started at %t ", coremark_start_time);
|
|
$display("");
|
|
$display("INFO-VERILOG: Be patient... there could be up to 90ms to simulate");
|
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$display("");
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|
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// Detect end of run
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// Detect end of run
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@(negedge p2_dout[1]);
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@(negedge p2_dout[1]);
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coremark_end_time = $time;
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coremark_end_time = $time;
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$timeformat(-3, 3, " ms", 10);
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$timeformat(-3, 3, " ms", 10);
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| Line 134... |
Line 143... |
|
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// Display stuff from the C-program
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// Display stuff from the C-program
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always @(p2_dout[0])
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always @(p2_dout[0])
|
begin
|
begin
|
$write("%s", p1_dout);
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$write("%s", p1_dout);
|
|
$fflush();
|
|
end
|
|
|
|
// Display some info to show simulation progress
|
|
initial
|
|
begin
|
|
@(posedge p2_dout[1]);
|
|
#1000000;
|
|
while (p2_dout[1])
|
|
begin
|
|
$display("INFO-VERILOG: Simulated time %t ", $time);
|
|
#1000000;
|
|
end
|
end
|
end
|
|
|
|
|
// Time tick counter
|
// Time tick counter
|
always @(negedge mclk or posedge puc_rst)
|
always @(negedge mclk or posedge puc_rst)
|
