/*===========================================================================*/
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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* Copyright (C) 2001 Authors */
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/* */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* disclaimer. */
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/* */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* (at your option) any later version. */
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/* */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* License for more details. */
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/* */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* COREMARK */
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/* COREMARK */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $Rev: 19 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define NO_TIMEOUT
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`define NO_TIMEOUT
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time mclk_start_time, mclk_end_time;
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time mclk_start_time, mclk_end_time;
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real mclk_period, mclk_frequency;
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real mclk_period, mclk_frequency;
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time coremark_start_time, coremark_end_time;
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time coremark_start_time, coremark_end_time;
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real coremark_per_sec;
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real coremark_per_sec;
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real coremark_per_mhz;
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real coremark_per_mhz;
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integer Number_Of_Iterations;
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integer Number_Of_Iterations;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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// Disable automatic DMA verification
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// Disable automatic DMA verification
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#10;
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#10;
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dma_verif_on = 0;
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dma_verif_on = 0;
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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//---------------------------------------
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//---------------------------------------
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// Check CPU configuration
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// Check CPU configuration
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//---------------------------------------
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//---------------------------------------
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if ((`PMEM_SIZE !== 55296) || (`DMEM_SIZE !== 5120))
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if ((`PMEM_SIZE !== 49152) || (`DMEM_SIZE !== 10240))
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION ERROR |");
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$display("| SIMULATION ERROR |");
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$display("| |");
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$display("| |");
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$display("| Core must be configured for: |");
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$display("| Core must be configured for: |");
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$display("| - 54kB program memory |");
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$display("| - 48kB program memory |");
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$display("| - 5kB data memory |");
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$display("| - 10kB data memory |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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end
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end
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// Disable watchdog
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// Disable watchdog
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// (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
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// (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
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`ifdef WATCHDOG
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`ifdef WATCHDOG
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force dut.watchdog_0.wdtcnt = 16'h0000;
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force dut.watchdog_0.wdtcnt = 16'h0000;
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`endif
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`endif
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//---------------------------------------
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//---------------------------------------
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// Number of benchmark iteration
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// Number of benchmark iteration
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// (Must match the C-code value)
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// (Must match the C-code value)
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//---------------------------------------
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//---------------------------------------
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Number_Of_Iterations = 1;
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Number_Of_Iterations = 1;
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//---------------------------------------
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//---------------------------------------
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// Measure clock period
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// Measure clock period
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//---------------------------------------
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//---------------------------------------
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repeat(100) @(posedge mclk);
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repeat(100) @(posedge mclk);
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$timeformat(-9, 3, " ns", 10);
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$timeformat(-9, 3, " ns", 10);
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@(posedge mclk);
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@(posedge mclk);
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mclk_start_time = $time;
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mclk_start_time = $time;
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@(posedge mclk);
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@(posedge mclk);
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mclk_end_time = $time;
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mclk_end_time = $time;
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@(posedge mclk);
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@(posedge mclk);
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mclk_period = mclk_end_time-mclk_start_time;
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mclk_period = mclk_end_time-mclk_start_time;
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mclk_frequency = 1000/mclk_period;
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mclk_frequency = 1000/mclk_period;
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$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz", mclk_frequency);
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$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz", mclk_frequency);
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//---------------------------------------
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//---------------------------------------
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// Measure CoreMark run time
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// Measure CoreMark run time
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//---------------------------------------
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//---------------------------------------
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// Detect beginning of run
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// Detect beginning of run
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@(posedge p2_dout[1]);
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@(posedge p2_dout[1]);
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coremark_start_time = $time;
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coremark_start_time = $time;
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$timeformat(-3, 3, " ms", 10);
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$timeformat(-3, 3, " ms", 10);
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$display("INFO-VERILOG: CoreMark loop started at %t ", coremark_start_time);
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$display("INFO-VERILOG: CoreMark loop started at %t ", coremark_start_time);
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$display("");
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$display("");
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$display("INFO-VERILOG: Be patient... there could be up to 90ms to simulate");
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$display("INFO-VERILOG: Be patient... there could be up to 90ms to simulate");
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$display("");
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$display("");
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// Detect end of run
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// Detect end of run
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@(negedge p2_dout[1]);
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@(negedge p2_dout[1]);
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coremark_end_time = $time;
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coremark_end_time = $time;
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$timeformat(-3, 3, " ms", 10);
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$timeformat(-3, 3, " ms", 10);
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$display("INFO-VERILOG: Coremark loop ended at %t ", coremark_end_time);
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$display("INFO-VERILOG: Coremark loop ended at %t ", coremark_end_time);
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// Compute results
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// Compute results
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$timeformat(-9, 3, " ns", 10);
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$timeformat(-9, 3, " ns", 10);
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coremark_per_sec = coremark_end_time - coremark_start_time;
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coremark_per_sec = coremark_end_time - coremark_start_time;
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coremark_per_sec = 1000000000 / coremark_per_sec;
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coremark_per_sec = 1000000000 / coremark_per_sec;
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coremark_per_sec = Number_Of_Iterations*coremark_per_sec;
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coremark_per_sec = Number_Of_Iterations*coremark_per_sec;
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coremark_per_mhz = coremark_per_sec / mclk_frequency;
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coremark_per_mhz = coremark_per_sec / mclk_frequency;
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// Report results
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// Report results
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$display("\INFO-VERILOG: CoreMark ticks : %d", {p6_din, p5_din, p4_din, p3_din});
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$display("\INFO-VERILOG: CoreMark ticks : %d", {p6_din, p5_din, p4_din, p3_din});
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$display("\INFO-VERILOG: CoreMark per second : %f", coremark_per_sec);
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$display("\INFO-VERILOG: CoreMark per second : %f", coremark_per_sec);
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$display("\INFO-VERILOG: CoreMark per MHz : %f\n\n", coremark_per_mhz);
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$display("\INFO-VERILOG: CoreMark per MHz : %f\n\n", coremark_per_mhz);
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//---------------------------------------
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//---------------------------------------
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// Wait for the end of C-code execution
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// Wait for the end of C-code execution
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//---------------------------------------
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//---------------------------------------
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@(posedge p2_dout[7]);
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@(posedge p2_dout[7]);
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stimulus_done = 1;
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stimulus_done = 1;
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| SIMULATION DONE |");
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$display("| SIMULATION DONE |");
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$display("| (stopped through verilog stimulus) |");
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$display("| (stopped through verilog stimulus) |");
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$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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end
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end
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// Display stuff from the C-program
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// Display stuff from the C-program
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always @(p2_dout[0])
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always @(p2_dout[0])
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begin
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begin
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$write("%s", p1_dout);
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$write("%s", p1_dout);
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$fflush();
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$fflush();
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end
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end
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// Display some info to show simulation progress
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// Display some info to show simulation progress
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initial
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initial
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begin
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begin
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@(posedge p2_dout[1]);
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@(posedge p2_dout[1]);
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#1000000;
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#1000000;
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while (p2_dout[1])
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while (p2_dout[1])
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begin
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begin
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$display("INFO-VERILOG: Simulated time %t ", $time);
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$display("INFO-VERILOG: Simulated time %t ", $time);
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#1000000;
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#1000000;
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end
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end
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end
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end
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// Time tick counter
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// Time tick counter
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always @(negedge mclk or posedge puc_rst)
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always @(negedge mclk or posedge puc_rst)
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if (puc_rst) {p6_din, p5_din, p4_din, p3_din} <= 32'h0000_0000;
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if (puc_rst) {p6_din, p5_din, p4_din, p3_din} <= 32'h0000_0000;
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else if (p2_dout[1]) {p6_din, p5_din, p4_din, p3_din} <= {p6_din, p5_din, p4_din, p3_din} + 32'h1;
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else if (p2_dout[1]) {p6_din, p5_din, p4_din, p3_din} <= {p6_din, p5_din, p4_din, p3_din} + 32'h1;
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