URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] [coremark_v1.0/] [msp430/] [linker.msp430-elf.x] - Diff between revs 200 and 211

Rev 200	Rev 211
Line 39...	Line 39...

`MEMORY {`	`MEMORY {`
`SFR : ORIGIN = 0x0000, LENGTH = 0x0010`	`SFR : ORIGIN = 0x0000, LENGTH = 0x0010`
`PERIPHERAL_8BIT : ORIGIN = 0x0010, LENGTH = 0x00F0`	`PERIPHERAL_8BIT : ORIGIN = 0x0010, LENGTH = 0x00F0`
`PERIPHERAL_16BIT : ORIGIN = 0x0100, LENGTH = 0x0100`	`PERIPHERAL_16BIT : ORIGIN = 0x0100, LENGTH = 0x0100`
`/* RAM : ORIGIN = 0x0200, LENGTH = 0x2800 /* 10kB */`	`RAM : ORIGIN = 0x0200, LENGTH = 0x2800 /* 10kB */`
`/* ROM (rx) : ORIGIN = 0x4000, LENGTH = 0xC000-0x20 /* 48kB */`	`ROM (rx) : ORIGIN = 0x4000, LENGTH = 0xC000-0x20 /* 48kB */`
`RAM : ORIGIN = 0x0200, LENGTH = 0x1400 /* 5kB */`
`ROM (rx) : ORIGIN = 0x2800, LENGTH = 0xD800-0x20 /* 54kB */`
`VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002`	`VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002`
`VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002`	`VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002`
`VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002`	`VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002`
`VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002`	`VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002`
`VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002`	`VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002`