URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] [coremark_v1.0/] [msp430/] [linker.msp430.x] - Diff between revs 200 and 211

Rev 200	Rev 211
Line 3...	Line 3...
`OUTPUT_ARCH("msp430")`	`OUTPUT_ARCH("msp430")`
`MEMORY {`	`MEMORY {`
`sfr : ORIGIN = 0x0000, LENGTH = 0x0010`	`sfr : ORIGIN = 0x0000, LENGTH = 0x0010`
`peripheral_8bit : ORIGIN = 0x0010, LENGTH = 0x00f0`	`peripheral_8bit : ORIGIN = 0x0010, LENGTH = 0x00f0`
`peripheral_16bit : ORIGIN = 0x0100, LENGTH = 0x0100`	`peripheral_16bit : ORIGIN = 0x0100, LENGTH = 0x0100`
	`ram (wx) : ORIGIN = 0x0200, LENGTH = 0x2800 /* 10kB */`
`/* ram (wx) : ORIGIN = 0x0200, LENGTH = 0x2800 /* 10kB */`	`rom (rx) : ORIGIN = 0x4000, LENGTH = 0xC000-0x20 /* 48kB */`
`/* rom (rx) : ORIGIN = 0x4000, LENGTH = 0xC000-0x20 /* 48kB */`

`ram (wx) : ORIGIN = 0x0200, LENGTH = 0x1400 /* 5kB */`
`rom (rx) : ORIGIN = 0x2800, LENGTH = 0xD800-0x20 /* 54kB */`
`vectors : ORIGIN = 0xffe0, LENGTH = 0x0020`	`vectors : ORIGIN = 0xffe0, LENGTH = 0x0020`
`}`	`}`
`REGION_ALIAS("REGION_TEXT", rom);`	`REGION_ALIAS("REGION_TEXT", rom);`
`REGION_ALIAS("REGION_DATA", ram);`	`REGION_ALIAS("REGION_DATA", ram);`
`PROVIDE (__info_segment_size = 0x80);`	`PROVIDE (__info_segment_size = 0x80);`