URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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| Rev 63 |
Rev 68 |
| Line 49... |
Line 49... |
{"Arria GX" EP1AGX50CF484C {6}}
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{"Arria GX" EP1AGX50CF484C {6}}
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{"Arria II GX" EP2AGX45DF29C {4 5 6}}
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{"Arria II GX" EP2AGX45DF29C {4 5 6}}
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{"Stratix" EP1S10F484C {5 6 7}}
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{"Stratix" EP1S10F484C {5 6 7}}
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{"Stratix II" EP2S15F484C {3 4 5}}
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{"Stratix II" EP2S15F484C {3 4 5}}
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{"Stratix III" EP3SE50F484C {2 3 4}}}
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{"Stratix III" EP3SE50F484C {2 3 4}}}
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set fpgaConfigs {{"Cyclone II" EP2C20F484C {7}}}
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# Set the different RTL configurations to be analysed
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# Set the different RTL configurations to be analysed
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set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3}
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set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}
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set rtlConfigs {{ 12 10 0 0 0 0 0 }
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set rtlConfigs {{ 12 10 0 0 0 0 0 0}
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{ 12 10 1 0 0 0 0 }
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{ 12 10 1 0 0 0 0 0}
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{ 12 10 1 1 0 0 0 }
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{ 12 10 1 1 0 0 0 0}
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{ 12 10 1 1 1 0 0 }
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{ 12 10 1 1 1 0 0 0}
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{ 12 10 1 1 1 1 0 }
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{ 12 10 1 1 1 1 0 0}
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{ 12 10 1 1 1 1 1 }}
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{ 12 10 1 1 1 1 1 0}}
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set rtlConfigs {{ 12 10 0 0 0 0 0 }}
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set rtlConfigs {{ 12 10 0 0 0 0 0 1}}
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# RTL configuration files
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# RTL configuration files
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set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
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set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
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set rtlConfigFile "./src/arch.v"
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set rtlConfigFile "./src/arch.v"
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