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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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Rev 56 |
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# READ DESING RTL #
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# READ DESING RTL #
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# #
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# #
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##############################################################################
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##############################################################################
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set DESIGN_NAME "openMSP430"
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set DESIGN_NAME "openMSP430"
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set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430.inc
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set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430.v
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../../rtl/verilog/openMSP430.v
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../../rtl/verilog/omsp_frontend.v
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../../rtl/verilog/cpu_frontend.v
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../../rtl/verilog/omsp_execution_unit.v
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../../rtl/verilog/cpu_execution_unit.v
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../../rtl/verilog/omsp_register_file.v
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../../rtl/verilog/cpu_register_file.v
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../../rtl/verilog/omsp_alu.v
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../../rtl/verilog/cpu_alu.v
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../../rtl/verilog/omsp_sfr.v
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../../rtl/verilog/mem_backbone.v
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../../rtl/verilog/omsp_clock_module.v
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../../rtl/verilog/sfr.v
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../../rtl/verilog/omsp_mem_backbone.v
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../../rtl/verilog/watchdog.v
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../../rtl/verilog/omsp_watchdog.v
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../../rtl/verilog/omsp_dbg.v
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../../rtl/verilog/omsp_dbg_uart.v
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../../rtl/verilog/omsp_dbg_hwbrk.v
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}
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}
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set_svf ./results/$DESIGN_NAME.svf
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set_svf ./results/$DESIGN_NAME.svf
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define_design_lib WORK -path ./WORK
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define_design_lib WORK -path ./WORK
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analyze -format verilog $RTL_SOURCE_FILES
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analyze -format verilog $RTL_SOURCE_FILES
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elaborate $DESIGN_NAME
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elaborate $DESIGN_NAME
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