| Line 12... |
Line 12... |
<li><a href="#2.1 Core"> 2.1 Core</a>
|
<li><a href="#2.1 Core"> 2.1 Core</a>
|
<ul>
|
<ul>
|
<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
|
<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
|
<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
|
<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
|
<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
|
<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
|
<li><a href="#2.1.4 Pinout"> 2.1.4 Pinout</a></li>
|
<ul>
|
<li><a href="#2.1.5 Instruction Cycles and Lengths">2.1.5 Instruction Cycles and Lengths</a></li>
|
<li><a href="#2.1.3.1 Basic System Configuration"> 2.1.3.1 Basic System Configuration</a></li>
|
<li><a href="#2.1.6 Serial Debug Interface"> 2.1.6 Serial Debug Interface</a></li>
|
<li><a href="#2.1.3.2 Advanced System Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
|
|
<li><a href="#2.1.3.3 Expert System Configuration"> 2.1.3.3 Expert System Configuration</a></li>
|
|
</ul>
|
|
<li><a href="#2.1.4 Memory mapping"> 2.1.4 Memory mapping</a></li>
|
|
<li><a href="#2.1.5 Pinout"> 2.1.5 Pinout</a></li>
|
|
<li><a href="#2.1.6 Instruction Cycles and Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
|
|
<li><a href="#2.1.7 Serial Debug Interface"> 2.1.7 Serial Debug Interface</a></li>
|
</ul>
|
</ul>
|
</li>
|
</li>
|
<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
|
<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
|
<ul>
|
<ul>
|
<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
|
<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
|
| Line 33... |
Line 39... |
</ul>
|
</ul>
|
|
|
<a name="1. Introduction"></a>
|
<a name="1. Introduction"></a>
|
<h1>1. Introduction</h1>
|
<h1>1. Introduction</h1>
|
|
|
The openMSP430 is a 16-bit microcontroller core compatible with TI's MSP430 family (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
|
The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b> (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
|
<br /><br />
|
<br /><br />
|
This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
|
This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
|
<br /><br />
|
<br /><br />
|
This IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
|
It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
|
However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
|
However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
|
<br /><br />
|
<br /><br />
|
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
|
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
|
<br /><br />
|
<br /><br />
|
|
|
| Line 64... |
Line 70... |
<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
|
<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
|
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
|
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
|
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
|
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
|
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
|
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
|
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
|
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
|
|
<li><b>16x16 Multiplier</b>: The hardware multiplier peripheral is transparently supported by the GCC compiler and is also located in the core. It can be included or excluded at will through a Verilog define.</li>
|
</ul>
|
</ul>
|
|
|
<a name="2.1.2 Limitations"></a>
|
<a name="2.1.2 Limitations"></a>
|
<h3>2.1.2 Limitations</h3>
|
<h3>2.1.2 Limitations</h3>
|
|
|
| Line 80... |
Line 87... |
</ul>
|
</ul>
|
|
|
<a name="2.1.3 Configuration"></a>
|
<a name="2.1.3 Configuration"></a>
|
<h3>2.1.3 Configuration</h3>
|
<h3>2.1.3 Configuration</h3>
|
|
|
It is possible to configure the openMSP430 core through the "openMSP430_defines.v" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
|
It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
|
Two sets of parameters can be adjusted by the user in order to define the program and data memory sizes:
|
Three sets of parameters can be adjusted by the user in order to fully customize the core.
|
|
|
|
<a name="2.1.3.1 Basic System Configuration"></a>
|
|
<h4>2.1.3.1 Basic System Configuration</h4>
|
|
|
|
The basic system can be adjusted with the following set of defines in order to match the target system requirements.
|
<br /><br />
|
<br /><br />
|
<table border="0" cellspacing="4" cellpadding="0">
|
<table border="0" cellspacing="4" cellpadding="0">
|
<tr>
|
<tr>
|
<td width="35"></td>
|
<td width="35"></td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td width="15"></td>
|
<td width="15"></td>
|
<td>
|
<td>
|
<code>
|
<code>
|
// Program Memory Size:
|
//============================================================================
|
|
<br />//============================================================================
|
|
<br />// BASIC SYSTEM CONFIGURATION
|
|
<br />//============================================================================
|
|
<br />//============================================================================
|
|
<br />//
|
|
<br />// Note: the sum of program, data and peripheral memory spaces must not
|
|
<br />// exceed 64 kB
|
|
<br />//
|
|
<br />
|
|
<br />// Program Memory Size:
|
<br />// Uncomment the required memory size
|
<br />// Uncomment the required memory size
|
<br />//-------------------------------------------------------
|
<br />//-------------------------------------------------------
|
<br />//`define PMEM_SIZE_59_KB
|
<br />//`define PMEM_SIZE_59_KB
|
<br />//`define PMEM_SIZE_55_KB
|
<br />//`define PMEM_SIZE_55_KB
|
<br />//`define PMEM_SIZE_54_KB
|
<br />//`define PMEM_SIZE_54_KB
|
| Line 124... |
Line 146... |
<br />//`define DMEM_SIZE_2_KB
|
<br />//`define DMEM_SIZE_2_KB
|
<br />//`define DMEM_SIZE_1_KB
|
<br />//`define DMEM_SIZE_1_KB
|
<br />//`define DMEM_SIZE_512_B
|
<br />//`define DMEM_SIZE_512_B
|
<br />//`define DMEM_SIZE_256_B
|
<br />//`define DMEM_SIZE_256_B
|
<br />`define DMEM_SIZE_128_B
|
<br />`define DMEM_SIZE_128_B
|
|
<br />
|
|
<br />// Include/Exclude Hardware Multiplier
|
|
<br />`define MULTIPLIER
|
|
<br />
|
|
<br />// Include/Exclude Serial Debug interface
|
|
<br />`define DBG_EN
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
</table>
|
</table>
|
<br /><br />
|
<br /><br />
|
<b>Note:</b> The sum of both program and data memories <b>SHOULD NOT</b> exceed 63.5 kB.
|
The only design considerations at this stage are:
|
<br /><br /><br />
|
<ul>
|
The following parameters define if the debug interface should be included or not and how many hardware breakpoint units should be included.
|
<li>Make sure that the program and data memories have the correct size :-P</li>
|
|
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
|
|
</ul>
|
|
<br />
|
|
|
|
<a name="2.1.3.2 Advanced System Configuration"></a>
|
|
<h4>2.1.3.2 Advanced System Configuration</h4>
|
|
|
|
In this section, some additional features are available in order to match the needs of more experienced users.
|
<br /><br />
|
<br /><br />
|
<table border="0" cellspacing="4" cellpadding="0">
|
<table border="0" cellspacing="4" cellpadding="0">
|
<tr>
|
<tr>
|
<td width="35"></td>
|
<td width="35"></td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td width="15"></td>
|
<td width="15"></td>
|
<td>
|
<td>
|
<code>
|
<code>
|
//----------------------------------------------------------------------------
|
//============================================================================
|
<br />// REMOTE DEBUGGING INTERFACE CONFIGURATION
|
<br />//============================================================================
|
<br />//----------------------------------------------------------------------------
|
<br />// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
|
|
<br />//============================================================================
|
|
<br />//============================================================================
|
<br />
|
<br />
|
<br />// Include Debug interface
|
<br />//-------------------------------------------------------
|
<br />`define DBG_EN
|
<br />// Peripheral Memory Space:
|
|
<br />//-------------------------------------------------------
|
|
<br />// The original MSP430 architecture map the peripherals
|
|
<br />// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
|
|
<br />// The following defines allow you to expand this space
|
|
<br />// up to 32 kB (i.e. from 0x0000 to 0x7fff).
|
|
<br />// As a consequence, the data memory mapping will be
|
|
<br />// shifted up and a custom linker script will therefore
|
|
<br />// be required by the GCC compiler.
|
|
<br />//-------------------------------------------------------
|
|
<br />//`define PER_SIZE_32_KB
|
|
<br />//`define PER_SIZE_16_KB
|
|
<br />//`define PER_SIZE_8_KB
|
|
<br />//`define PER_SIZE_4_KB
|
|
<br />//`define PER_SIZE_2_KB
|
|
<br />//`define PER_SIZE_1_KB
|
|
<br />`define PER_SIZE_512_B
|
<br />
|
<br />
|
<br />// Debug interface selection
|
|
<br />// `define DBG_UART -> Enable UART (8N1) debug interface
|
|
<br />// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
|
|
<br />//
|
|
<br />`define DBG_UART
|
|
<br />//`define DBG_JTAG
|
|
<br />
|
<br />
|
<br />// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
|
<br />//-------------------------------------------------------
|
<br />// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
|
<br />// Defines the debugger CPU_CTL.RST_BRK_EN reset value
|
<br />// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
|
<br />// (CPU break on PUC reset)
|
<br />// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
|
<br />//-------------------------------------------------------
|
<br />// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
|
<br />// When defined, the CPU will automatically break after
|
<br />//
|
<br />// a PUC occurrence by default. This is typically usefull
|
<br />`define DBG_HWBRK_0
|
<br />// when the program memory can only be initialized through
|
<br />`define DBG_HWBRK_1
|
<br />// the serial debug interface.
|
<br />`define DBG_HWBRK_2
|
<br />//-------------------------------------------------------
|
<br />`define DBG_HWBRK_3
|
<br />//`define DBG_RST_BRK_EN
|
|
<br />
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Custom user version number
|
|
<br />//-------------------------------------------------------
|
|
<br />// This 5 bit field can be freely used in order to allow
|
|
<br />// custom identification of the system through the debug
|
|
<br />// interface.
|
|
<br />// (see CPU_ID.USER_VERSION field in the documentation)
|
|
<br />//-------------------------------------------------------
|
|
<br />`define USER_VERSION 5'b00000
|
|
<br />
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
</table>
|
</table>
|
<br /><br />
|
<br /><br />
|
<b>Note:</b> Since the hardware breakpoint units are relatively big, it is recommended to include as many as you plan to use. These units are particularly useful if your instruction memory is a ROM (i.e. when you can't use software breakpoints) or if you want to be able to stop the CPU whenever some particular data addresses are accessed.
|
Design consideration at this stage are:
|
<br /><br /><br />
|
<ul>
|
At last, this parameter controls if the hardware multiplier is included or not.
|
<li>Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.</li>
|
|
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
|
|
</ul>
|
|
<br />
|
|
<a name="2.1.3.3 Expert System Configuration"></a>
|
|
<h4>2.1.3.3 Expert System Configuration</h4>
|
|
|
|
In this section, you will find configuration options which will be relevant for roughly 0.01% of the users (according to an highly reliable market analysis ;-) ).
|
<br /><br />
|
<br /><br />
|
<table border="0" cellspacing="4" cellpadding="0">
|
<table border="0" cellspacing="4" cellpadding="0">
|
<tr>
|
<tr>
|
<td width="35"></td>
|
<td width="35"></td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td width="15"></td>
|
<td width="15"></td>
|
<td>
|
<td>
|
<code>
|
<code>
|
// Include/Exclude Hardware Multiplier
|
//============================================================================
|
<br />`define MULTIPLIER
|
<br />//============================================================================
|
|
<br />// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
|
|
<br />//============================================================================
|
|
<br />//============================================================================
|
|
<br />//
|
|
<br />// IMPORTANT NOTE: Please update following configuration options ONLY if
|
|
<br />// you have a good reason to do so... and if you know what
|
|
<br />// you are doing :-P
|
|
<br />//
|
|
<br />//============================================================================
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Number of hardware breakpoint units (each unit contains
|
|
<br />// two hardware address breakpoints):
|
|
<br />// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
|
|
<br />// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
|
|
<br />// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
|
|
<br />// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
|
|
<br />//-------------------------------------------------------
|
|
<br />// Please keep in mind that hardware breakpoints only
|
|
<br />// make sense whenever the program memory is not an SRAM
|
|
<br />// (i.e. Flash/OTP/ROM/...) or when you are interested
|
|
<br />// in data breakpoints (btw. not supported by GDB).
|
|
<br />//-------------------------------------------------------
|
|
<br />//`define DBG_HWBRK_0
|
|
<br />//`define DBG_HWBRK_1
|
|
<br />//`define DBG_HWBRK_2
|
|
<br />//`define DBG_HWBRK_3
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Enable/Disable the hardware breakpoint RANGE mode
|
|
<br />//-------------------------------------------------------
|
|
<br />// When enabled this feature allows the hardware breakpoint
|
|
<br />// units to stop the cpu whenever an instruction or data
|
|
<br />// access lays within an address range.
|
|
<br />// Note that this feature is not supported by GDB.
|
|
<br />//-------------------------------------------------------
|
|
<br />//`define DBG_HWBRK_RANGE
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Input synchronizers
|
|
<br />//-------------------------------------------------------
|
|
<br />// In some cases, the asynchronous input ports might
|
|
<br />// already be synchronized externally.
|
|
<br />// If an extensive CDC design review showed that this
|
|
<br />// is really the case, the individual synchronizers
|
|
<br />// can be disabled with the following defines.
|
|
<br />//
|
|
<br />// Notes:
|
|
<br />// - the dbg_en signal will reset the debug interface
|
|
<br />// when 0. Therefore make sure it is glitch free.
|
|
<br />//
|
|
<br />// - the dbg_uart_rxd synchronizer must be set to 1
|
|
<br />// when its reset is active.
|
|
<br />//-------------------------------------------------------
|
|
<br />`define SYNC_CPU_EN
|
|
<br />`define SYNC_DBG_EN
|
|
<br />`define SYNC_DBG_UART_RXD
|
|
<br />`define SYNC_NMI
|
|
<br />
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
</table>
|
</table>
|
<br /><br /><br />
|
<br /><br />
|
All remaining defines located in this file are system constants and should not be edited.
|
Design consideration at this stage are:
|
|
<ul>
|
|
<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
|
|
</ul>
|
|
<br />
|
|
All remaining defines located in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
|
|
<br /><br />
|
|
|
|
<a name="2.1.4 Memory mapping"></a>
|
|
<h3>2.1.4 Memory mapping</h3>
|
|
|
<a name="2.1.4 Pinout"></a>
|
As discussed in the earlier section, the openMSP430 memory mapping is fully configurable.<br />
|
<h3>2.1.4 Pinout</h3>
|
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC4 (or any other toolchain for that matter).<br />
|
|
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section give the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.<br />
|
|
The following schematic should hopefully summarize this:<br />
|
|
<br /><br />
|
|
<img src="usercontent,img,1306066277" width="100%" alt="Memory mapping" title="Memory mapping" />
|
|
<br />
|
|
|
|
<br /><br />
|
|
<a name="2.1.5 Pinout"></a>
|
|
<h3>2.1.5 Pinout</h3>
|
|
|
The full pinout of the openMSP430 core is provided in the following table:
|
The full pinout of the openMSP430 core is provided in the following table:
|
<br /><br />
|
<br /><br />
|
<table border="1">
|
<table border="1">
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
|
<tr>
|
<tr>
|
|
<td> cpu_en </td>
|
|
<td> Input </td>
|
|
<td> 1 </td>
|
|
<td> Enable CPU code execution (asynchronous) - set to 1 if unused </td>
|
|
</tr>
|
|
<tr>
|
<td> dco_clk </td>
|
<td> dco_clk </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Fast oscillator (fast clock), CPU clock </td>
|
<td> Fast oscillator (fast clock), CPU clock </td>
|
</tr>
|
</tr>
|
| Line 232... |
Line 381... |
<td> SMCLK enable </td>
|
<td> SMCLK enable </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> puc </td>
|
<td> puc_rst </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Main system reset </td>
|
<td> Main system reset </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> reset_n </td>
|
<td> reset_n </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Reset Pin (low active) </td>
|
<td> Reset Pin (active low, asynchronous) </td>
|
</tr>
|
</tr>
|
|
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> pmem_addr </td>
|
<td> pmem_addr </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> `PMEM_AWIDTH<sup>1</sup> </td>
|
<td> `PMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b> </td>
|
<td> Program Memory address </td>
|
<td> Program Memory address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_cen </td>
|
<td> pmem_cen </td>
|
<td> Output </td>
|
<td> Output </td>
|
| Line 262... |
Line 411... |
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_din </td>
|
<td> pmem_din </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
<td> Program Memory data input (optional<sup>2</sup>) </td>
|
<td> Program Memory data input (optional <b><sup><font color="#FF0000">2</font></sup></b>)</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_dout </td>
|
<td> pmem_dout </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
| Line 274... |
Line 423... |
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_wen </td>
|
<td> pmem_wen </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 2 </td>
|
<td> 2 </td>
|
<td> Program Memory write enable (low active) (optional<sup>2</sup>) </td>
|
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#FF0000">2</font></sup></b>) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> dmem_addr </td>
|
<td> dmem_addr </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> `DMEM_AWIDTH<sup>1</sup> </td>
|
<td> `DMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b></td>
|
<td> Data Memory address </td>
|
<td> Data Memory address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dmem_cen </td>
|
<td> dmem_cen </td>
|
<td> Output </td>
|
<td> Output </td>
|
| Line 306... |
Line 455... |
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dmem_wen </td>
|
<td> dmem_wen </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 2 </td>
|
<td> 2 </td>
|
<td> Data Memory write enable (low active) </td>
|
<td> Data Memory write byte enable (low active) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> per_addr </td>
|
<td> per_addr </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 8 </td>
|
<td> 14 </td>
|
<td> Peripheral address </td>
|
<td> Peripheral address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> per_din </td>
|
<td> per_din </td>
|
<td> Output </td>
|
<td> Output </td>
|
| Line 335... |
Line 484... |
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Peripheral enable (high active) </td>
|
<td> Peripheral enable (high active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> per_wen </td>
|
<td> per_we </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 2 </td>
|
<td> 2 </td>
|
<td> Peripheral write enable (high active) </td>
|
<td> Peripheral write enable (high active) </td>
|
</tr>
|
</tr>
|
|
|
| Line 363... |
Line 512... |
<td> Interrupt request accepted (one-hot signal) </td>
|
<td> Interrupt request accepted (one-hot signal) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
|
<td> dbg_en </td>
|
|
<td> Input </td>
|
|
<td> 1 </td>
|
|
<td> Debug interface enable (asynchronous) <b><sup><font color="#FF0000">3</font></sup></b> </td>
|
|
</tr>
|
|
<tr>
|
<td> dbg_freeze </td>
|
<td> dbg_freeze </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Freeze peripherals </td>
|
<td> Freeze peripherals </td>
|
</tr>
|
</tr>
|
| Line 378... |
Line 533... |
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dbg_uart_rxd </td>
|
<td> dbg_uart_rxd </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Debug interface: UART RXD </td>
|
<td> Debug interface: UART RXD (asynchronous) </td>
|
</tr>
|
</tr>
|
</table>
|
</table>
|
<br />
|
<br />
|
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
|
<b><sup><font color="#FF0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
|
<sup>2</sup>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.
|
<b><sup><font color="#FF0000">2</font></sup></b>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.<br />
|
<br /><br />
|
<b><sup><font color="#FF0000">3</font></sup></b>: When disabled, the debug interface is hold into reset. As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br />
|
|
<br />
|
|
|
<a name="2.1.5 Instruction Cycles and Lengths"></a>
|
<a name="2.1.6 Instruction Cycles and Lengths"></a>
|
<h3>2.1.5 Instruction Cycles and Lengths</h3>
|
<h3>2.1.6 Instruction Cycles and Lengths</h3>
|
|
|
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.
|
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br /><br />
|
<br />In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.<br />
|
|
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
Differences with the original MSP430 are highlighted in green (the original value being red).
|
Differences with the original MSP430 are highlighted in green (the original value being red).
|
<ul>
|
<ul>
|
<li><b>Interrupt and Reset Cycles</b></li>
|
<li><b>Interrupt and Reset Cycles</b></li>
|
</ul>
|
</ul>
|
<table border="1">
|
<table border="1">
|
| Line 468... |
Line 625... |
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
</table>
|
</table>
|
|
|
<a name="2.1.6 Serial Debug Interface"></a>
|
<a name="2.1.7 Serial Debug Interface"></a>
|
<h3>2.1.6 Serial Debug Interface</h3>
|
<h3>2.1.7 Serial Debug Interface</h3>
|
|
|
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
|
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
|
<a name="2.2 Peripherals"></a>
|
<a name="2.2 Peripherals"></a>
|
<h2>2.2 Peripherals</h2>
|
<h2>2.2 Peripherals</h2>
|
|
|
| Line 504... |
Line 661... |
<td width="15"></td>
|
<td width="15"></td>
|
<td>
|
<td>
|
<code>
|
<code>
|
reg [7:0] test_cnt;
|
reg [7:0] test_cnt;
|
<br />
|
<br />
|
<br />always @ (posedge mclk or posedge puc)
|
<br />always @ (posedge mclk or posedge puc_rst)
|
<br /> if (puc) test_cnt <= 8'h00;
|
<br /> if (puc_rst) test_cnt <= 8'h00;
|
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
</table>
|
</table>
|
| Line 588... |
Line 745... |
<br /><br />
|
<br /><br />
|
<table border="1">
|
<table border="1">
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
|
| Line 645... |
Line 802... |
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
|
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
|
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
|
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
|
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
|
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
|
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
|
