this signal selects which byte should be written during a valid access.
this signal selects which byte should be written during a valid access.
PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on
PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on
the upper byte. Note that these signals are HIGH ACTIVE. <br><br>
the upper byte. Note that these signals are HIGH ACTIVE. <br><br>
</li>
</li>
<li>
<li>
<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WEN</i> value.
<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WE</i> value.
<br><br>
<br><br>
</li>
</li>
</ul>
</ul>
The following waveform illustrates some read/write access to the peripheral registers:<br><br>
The following waveform illustrates some read/write access to the peripheral registers:<br><br>
<img src="http://opencores.org/usercontent,img,1263320825" alt="Waveforms: Peripherals - Jan 12." title="Waveforms: Peripherals - Jan 12." width="100%">
<img src="http://opencores.org/usercontent,img,1263320825" alt="Waveforms: Peripherals - Jan 12." title="Waveforms: Peripherals - Jan 12." width="100%">
