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The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is
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The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is
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compatible with Texas Instruments' <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430 microcontroller
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compatible with Texas Instruments' <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430 microcontroller
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family</a></b> and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.<br>
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family</a></b> and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.<br>
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<br>
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<br>
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The core comes with some peripherals (<b>16x16 Hardware Multiplier, </b>Watchdog,
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The core comes with some peripherals (<b>16x16 Hardware Multiplier, </b>Watchdog,
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GPIO, TimerA, generic templates) and most notably with a two-wire <b>Serial
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GPIO, TimerA, generic templates), with a DMA interface, and most notably with a two-wire <b>Serial
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Debug Interface</b> supporting the<b> <a href="http://sourceforge.net/apps/mediawiki/mspgcc/index.php?title=MSPGCC_Wiki" target="_blank">MSPGCC</a> GNU Debugger</b> (GDB) for in-system
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Debug Interface</b> supporting the<b> <a href="http://sourceforge.net/apps/mediawiki/mspgcc/index.php?title=MSPGCC_Wiki" target="_blank">MSPGCC</a> GNU Debugger</b> (GDB) for in-system
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software debugging. <br>
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software debugging. <br>
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<br>
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<br>
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While being fully FPGA friendly, this design is also particularly
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While being fully FPGA friendly, this design is also particularly
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suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements).<br>
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suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements).<br>
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<li>Full instruction set support.</li>
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<li>Full instruction set support.</li>
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<li>Interrupts: IRQs (x14, x30 or x62), NMI (x1).</li>
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<li>Interrupts: IRQs (x14, x30 or x62), NMI (x1).</li>
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<li>Low Power Modes (LPMx).</li>
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<li>Low Power Modes (LPMx).</li>
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<li>Configurable memory size for both program and data.</li>
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<li>Configurable memory size for both program and data.</li>
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<li>Scalable peripheral address space.</li>
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<li>Scalable peripheral address space.</li>
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<li>DMA interface.</li>
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<li>Two-wire Serial Debug Interface (I<sup>2</sup>C or UART based) with GDB support (Nexus class 3, w/o trace).</li>
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<li>Two-wire Serial Debug Interface (I<sup>2</sup>C or UART based) with GDB support (Nexus class 3, w/o trace).</li>
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<li>FPGA friendly (option for single clock domain, no clock gate).</li>
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<li>FPGA friendly (option for single clock domain, no clock gate).</li>
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<li>ASIC friendly (options for full power & clock management support).<br>
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<li>ASIC friendly (options for full power & clock management support).<br>
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</li>
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</li>
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