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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_uart.v] - Diff between revs 104 and 105

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Rev 104 Rev 105
Line 90... Line 90...
 
 
// Synchronize RXD input & buffer
// Synchronize RXD input & buffer
//--------------------------------
//--------------------------------
reg  [3:0] rxd_sync;
reg  [3:0] rxd_sync;
always @ (posedge mclk or posedge por)
always @ (posedge mclk or posedge por)
  if (por) rxd_sync <=  4'h0;
  if (por) rxd_sync <=  4'hf;
  else     rxd_sync <=  {rxd_sync[2:0], dbg_uart_rxd};
  else     rxd_sync <=  {rxd_sync[2:0], dbg_uart_rxd};
 
 
// Majority decision
// Majority decision
//------------------------
//------------------------
reg        rxd_maj;
reg        rxd_maj;

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