| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev$
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy$
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 165... |
Line 165... |
`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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wire mclk_wdtctl;
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wire mclk_wdtctl;
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omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
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omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
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.clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
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.clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
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`else
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`else
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wire UNUSED_scan_enable = scan_enable;
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wire mclk_wdtctl = mclk;
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wire mclk_wdtctl = mclk;
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`endif
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`endif
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`ifdef NMI
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`ifdef NMI
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parameter [7:0] WDTNMIES_MASK = 8'h40;
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parameter [7:0] WDTNMIES_MASK = 8'h40;
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| Line 240... |
Line 241... |
.clk_out (wdt_clk),
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.clk_out (wdt_clk),
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.clk_in0 (smclk),
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.clk_in0 (smclk),
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.clk_in1 (aclk),
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.clk_in1 (aclk),
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.reset (puc_rst),
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.reset (puc_rst),
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.scan_mode (scan_mode),
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.scan_mode (scan_mode),
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.select (wdtctl[2])
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.select_in (wdtctl[2])
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);
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);
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`else
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`else
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`ifdef WATCHDOG_NOMUX_ACLK
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`ifdef WATCHDOG_NOMUX_ACLK
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assign wdt_clk = aclk;
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assign wdt_clk = aclk;
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wire UNUSED_smclk = smclk;
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`else
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`else
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wire UNUSED_aclk = aclk;
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assign wdt_clk = smclk;
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assign wdt_clk = smclk;
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`endif
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`endif
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`endif
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`endif
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|
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// Reset synchronizer for the watchdog local clock domain
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// Reset synchronizer for the watchdog local clock domain
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| Line 469... |
Line 472... |
always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) wdt_reset <= 1'b0;
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if (por) wdt_reset <= 1'b0;
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else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
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else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
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// LINT cleanup
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wire UNUSED_smclk_en = smclk_en;
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wire UNUSED_aclk_en = aclk_en;
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|
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//=============================================================================
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//=============================================================================
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// 6) WATCHDOG TIMER (FPGA IMPLEMENTATION)
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// 6) WATCHDOG TIMER (FPGA IMPLEMENTATION)
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//=============================================================================
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//=============================================================================
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`else
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`else
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| Line 543... |
Line 550... |
always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) wdt_reset <= 1'b0;
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if (por) wdt_reset <= 1'b0;
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else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
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else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
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|
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// LINT cleanup
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wire UNUSED_scan_mode = scan_mode;
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wire UNUSED_smclk = smclk;
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wire UNUSED_aclk = aclk;
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`endif
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`endif
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wire [15:0] UNUSED_per_din = per_din;
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|
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endmodule // omsp_watchdog
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endmodule // omsp_watchdog
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|
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`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
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`else
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`else
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