URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Diff between revs 202 and 204

Rev 202	Rev 204
Line 782...	Line 782...
`define BRK_RANGE 4	`define BRK_RANGE 4

`// Basic clock module: BCSCTL1 Control Register`	`// Basic clock module: BCSCTL1 Control Register`
`define DIVAx 5:4	`define DIVAx 5:4
`define DMA_CPUOFF 0	`define DMA_CPUOFF 0
`define DMA_SCG0 1	`define DMA_OSCOFF 1
`define DMA_SCG1 2	`define DMA_SCG0 2
`define DMA_OSCOFF 3	`define DMA_SCG1 3

`// Basic clock module: BCSCTL2 Control Register`	`// Basic clock module: BCSCTL2 Control Register`
`define SELMx 7	`define SELMx 7
`define DIVMx 5:4	`define DIVMx 5:4
`define SELS 3	`define SELS 3