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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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| Rev 94 |
Rev 98 |
| Line 41... |
Line 41... |
EXPECTED_ARGS=3
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EXPECTED_ARGS=3
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if [ $# -ne $EXPECTED_ARGS ]; then
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if [ $# -ne $EXPECTED_ARGS ]; then
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echo "ERROR : wrong number of arguments"
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echo "ERROR : wrong number of arguments"
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echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
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echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
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echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
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echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
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echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog"
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echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog/vsim/vcs"
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exit 1
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exit 1
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fi
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fi
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###############################################################################
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###############################################################################
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| Line 96... |
Line 96... |
cver* )
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cver* )
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vargs="$vargs +define+VXL" ;;
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vargs="$vargs +define+VXL" ;;
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verilog* )
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verilog* )
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vargs="$vargs +define+VXL" ;;
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vargs="$vargs +define+VXL" ;;
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ncverilog* )
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ncverilog* )
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vargs="$vargs +access+r" ;;
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rm -rf INCA_libs
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vargs="$vargs +access+r +define+TRN_FILE" ;;
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vcs* )
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rm -rf csrc simv*
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vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
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vsim )
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vsim )
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# Modelsim
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# Modelsim
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if [ -d work ]; then vdel -all; fi
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if [ -d work ]; then vdel -all; fi
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vlib work
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vlib work
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exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all"
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exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all"
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