| Line 175... |
Line 175... |
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
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.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
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.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
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.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.dma_dout (), // Direct Memory Access data output
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.dma_ready (), // Direct Memory Access is complete
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.dma_resp (), // Direct Memory Access response (0:Okay / 1:Error)
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_addr (pmem_addr), // Program Memory address
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| Line 199... |
Line 202... |
.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
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.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_bus), // Maskable interrupts
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.irq (irq_bus), // Maskable interrupts
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.dma_addr (15'h0000), // Direct Memory Access address
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.dma_din (16'h0000), // Direct Memory Access data input
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.dma_en (1'b0), // Direct Memory Access enable (high active)
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.dma_priority (1'b0), // Direct Memory Access priority (0:low / 1:high)
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.dma_we (2'b00), // Direct Memory Access write byte enable (high active)
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.dma_wkup (1'b0), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.per_dout (per_dout), // Peripheral data output
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.per_dout (per_dout), // Peripheral data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
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.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
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.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
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.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
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| Line 339... |
Line 348... |
irq_port1}; // Vector 0 (0xFFE0)
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irq_port1}; // Vector 0 (0xFFE0)
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endmodule // omsp_system_1
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endmodule // omsp_system_1
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