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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [sim/] [rtl_sim/] [src/] [submit.f] - Diff between revs 202 and 212

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Rev 202 Rev 212
Line 51... Line 51...
//=============================================================================
//=============================================================================
// Xilinx library
// Xilinx library
//=============================================================================
//=============================================================================
+libext+.v
+libext+.v
 
 
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/
-y /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/simprims/
-y /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/
-y /cad/Xilinx/14.7/ISE_DS/ISE/verilog/src/XilinxCoreLib/
 
 
 
 
//=============================================================================
//=============================================================================
// FPGA Specific modules
// FPGA Specific modules
//=============================================================================
//=============================================================================

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