URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 94 and 98

Rev 94	Rev 98
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 94 $`	`// $Rev: 98 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $`	`// $LastChangedDate: 2011-02-28 21:20:51 +0100 (Mon, 28 Feb 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`include "timescale.v"	`include "timescale.v"
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"

`module tb_openMSP430_fpga;`	`module tb_openMSP430_fpga;`
Line 325...	Line 325...
`begin`	`begin`
`ifdef VPD_FILE	`ifdef VPD_FILE
`$vcdplusfile("tb_openMSP430_fpga.vpd");`	`$vcdplusfile("tb_openMSP430_fpga.vpd");`
`$vcdpluson();`	`$vcdpluson();`
`else	`else
	`ifdef TRN_FILE
	`$recordfile ("tb_openMSP430_fpga.trn");`
	`$recordvars;`
	`else
`$dumpfile("tb_openMSP430_fpga.vcd");`	`$dumpfile("tb_openMSP430_fpga.vcd");`
`$dumpvars(0, tb_openMSP430_fpga);`	`$dumpvars(0, tb_openMSP430_fpga);`
`endif	`endif
	`endif
`end`	`end`

`//`	`//`
`// End of simulation`	`// End of simulation`
`//----------------------------------------`	`//----------------------------------------`