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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [omsp_uart.v] - Diff between revs 197 and 202

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Rev 197 Rev 202
Line 295... Line 295...
//--------------------------------
//--------------------------------
wire     uart_rxd_sync_n;
wire     uart_rxd_sync_n;
 
 
omsp_sync_cell sync_cell_uart_rxd (
omsp_sync_cell sync_cell_uart_rxd (
    .data_out  (uart_rxd_sync_n),
    .data_out  (uart_rxd_sync_n),
    .data_meta (),
 
    .data_in   (~uart_rxd),
    .data_in   (~uart_rxd),
    .clk       (mclk),
    .clk       (mclk),
    .rst       (puc_rst)
    .rst       (puc_rst)
);
);
wire uart_rxd_sync = ~uart_rxd_sync_n;
wire uart_rxd_sync = ~uart_rxd_sync_n;
Line 487... Line 486...
                         (status_tx_empty_pnd & ctrl_ien_tx_empty);
                         (status_tx_empty_pnd & ctrl_ien_tx_empty);
 
 
 
 
endmodule // uart
endmodule // uart
 
 
 
 
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