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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_clock_gate.v] - Diff between revs 136 and 202

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Rev 136 Rev 202
Line 81... Line 81...
assign  gclk      =  (clk & enable_latch);
assign  gclk      =  (clk & enable_latch);
 
 
 
 
endmodule // omsp_clock_gate
endmodule // omsp_clock_gate
 
 
 
 
 
 
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