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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_i2c.v] - Diff between revs 188 and 202

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Rev 188 Rev 202
Line 59... Line 59...
    dbg_dout,                          // Debug register data output
    dbg_dout,                          // Debug register data output
    dbg_i2c_addr,                      // Debug interface: I2C ADDRESS
    dbg_i2c_addr,                      // Debug interface: I2C ADDRESS
    dbg_i2c_broadcast,                 // Debug interface: I2C Broadcast Address (for multicore systems)
    dbg_i2c_broadcast,                 // Debug interface: I2C Broadcast Address (for multicore systems)
    dbg_i2c_scl,                       // Debug interface: I2C SCL
    dbg_i2c_scl,                       // Debug interface: I2C SCL
    dbg_i2c_sda_in,                    // Debug interface: I2C SDA IN
    dbg_i2c_sda_in,                    // Debug interface: I2C SDA IN
    dbg_rd_rdy,                        // Debug register data is ready for read
 
    dbg_rst,                           // Debug unit reset
    dbg_rst,                           // Debug unit reset
    mem_burst,                         // Burst on going
    mem_burst,                         // Burst on going
    mem_burst_end,                     // End TX/RX burst
    mem_burst_end,                     // End TX/RX burst
    mem_burst_rd,                      // Start TX burst
    mem_burst_rd,                      // Start TX burst
    mem_burst_wr,                      // Start RX burst
    mem_burst_wr,                      // Start RX burst
Line 84... Line 83...
input        [15:0] dbg_dout;          // Debug register data output
input        [15:0] dbg_dout;          // Debug register data output
input         [6:0] dbg_i2c_addr;      // Debug interface: I2C ADDRESS
input         [6:0] dbg_i2c_addr;      // Debug interface: I2C ADDRESS
input         [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input         [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input               dbg_i2c_scl;       // Debug interface: I2C SCL
input               dbg_i2c_scl;       // Debug interface: I2C SCL
input               dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
input               dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
input               dbg_rd_rdy;        // Debug register data is ready for read
 
input               dbg_rst;           // Debug unit reset
input               dbg_rst;           // Debug unit reset
input               mem_burst;         // Burst on going
input               mem_burst;         // Burst on going
input               mem_burst_end;     // End TX/RX burst
input               mem_burst_end;     // End TX/RX burst
input               mem_burst_rd;      // Start TX burst
input               mem_burst_rd;      // Start TX burst
input               mem_burst_wr;      // Start RX burst
input               mem_burst_wr;      // Start RX burst
Line 312... Line 310...
assign i2c_addr_not_valid =  (i2c_state == RX_ADDR) && shift_rx_done && (
assign i2c_addr_not_valid =  (i2c_state == RX_ADDR) && shift_rx_done && (
`ifdef DBG_I2C_BROADCAST
`ifdef DBG_I2C_BROADCAST
                              (shift_buf[7:1] != dbg_i2c_broadcast[6:0]) &&
                              (shift_buf[7:1] != dbg_i2c_broadcast[6:0]) &&
`endif
`endif
                              (shift_buf[7:1] != dbg_i2c_addr[6:0]));
                              (shift_buf[7:1] != dbg_i2c_addr[6:0]));
 
`ifdef DBG_I2C_BROADCAST
 
`else
 
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
 
`endif
 
 
// Utility signals
// Utility signals
wire        shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA);
wire        shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA);
wire        shift_tx_data_done = shift_tx_done;
wire        shift_tx_data_done = shift_tx_done;
 
 

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